MC_SEQ_RAS_TIMING_LP 5886 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		*out_reg = MC_SEQ_RAS_TIMING_LP;
MC_SEQ_RAS_TIMING_LP 5999 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
MC_SEQ_RAS_TIMING_LP 1862 drivers/gpu/drm/radeon/btc_dpm.c 		*out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
MC_SEQ_RAS_TIMING_LP 2031 drivers/gpu/drm/radeon/btc_dpm.c 	WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
MC_SEQ_RAS_TIMING_LP 4413 drivers/gpu/drm/radeon/ci_dpm.c 		*out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
MC_SEQ_RAS_TIMING_LP 4636 drivers/gpu/drm/radeon/ci_dpm.c 	WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
MC_SEQ_RAS_TIMING_LP  972 drivers/gpu/drm/radeon/cypress_dpm.c 	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RAS_TIMING_LP >> 2;
MC_SEQ_RAS_TIMING_LP 2774 drivers/gpu/drm/radeon/ni_dpm.c 		*out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
MC_SEQ_RAS_TIMING_LP 2883 drivers/gpu/drm/radeon/ni_dpm.c 	WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
MC_SEQ_RAS_TIMING_LP 5432 drivers/gpu/drm/radeon/si_dpm.c 		*out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
MC_SEQ_RAS_TIMING_LP 5545 drivers/gpu/drm/radeon/si_dpm.c 	WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));