MC_SEQ_PMG_CMD_MRS2_LP 5922 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		*out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
MC_SEQ_PMG_CMD_MRS2_LP 6011 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
MC_SEQ_PMG_CMD_MRS2_LP 4467 drivers/gpu/drm/radeon/ci_dpm.c 		*out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
MC_SEQ_PMG_CMD_MRS2_LP 4654 drivers/gpu/drm/radeon/ci_dpm.c 	WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
MC_SEQ_PMG_CMD_MRS2_LP 2810 drivers/gpu/drm/radeon/ni_dpm.c 		*out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
MC_SEQ_PMG_CMD_MRS2_LP 2895 drivers/gpu/drm/radeon/ni_dpm.c 	WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
MC_SEQ_PMG_CMD_MRS2_LP 5468 drivers/gpu/drm/radeon/si_dpm.c 		*out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
MC_SEQ_PMG_CMD_MRS2_LP 5557 drivers/gpu/drm/radeon/si_dpm.c 	WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));