MC_SEQ_PMG_CMD_MRS1_LP 5864 drivers/gpu/drm/amd/amdgpu/si_dpm.c 			table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
MC_SEQ_PMG_CMD_MRS1_LP 5916 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		*out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
MC_SEQ_PMG_CMD_MRS1_LP 6005 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
MC_SEQ_PMG_CMD_MRS1_LP 1892 drivers/gpu/drm/radeon/btc_dpm.c 		*out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
MC_SEQ_PMG_CMD_MRS1_LP 1958 drivers/gpu/drm/radeon/btc_dpm.c 			table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
MC_SEQ_PMG_CMD_MRS1_LP 2041 drivers/gpu/drm/radeon/btc_dpm.c 	WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
MC_SEQ_PMG_CMD_MRS1_LP 4387 drivers/gpu/drm/radeon/ci_dpm.c 			table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
MC_SEQ_PMG_CMD_MRS1_LP 4461 drivers/gpu/drm/radeon/ci_dpm.c 		*out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
MC_SEQ_PMG_CMD_MRS1_LP 4648 drivers/gpu/drm/radeon/ci_dpm.c 	WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
MC_SEQ_PMG_CMD_MRS1_LP 1012 drivers/gpu/drm/radeon/cypress_dpm.c 	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
MC_SEQ_PMG_CMD_MRS1_LP 2749 drivers/gpu/drm/radeon/ni_dpm.c 			table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
MC_SEQ_PMG_CMD_MRS1_LP 2804 drivers/gpu/drm/radeon/ni_dpm.c 		*out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
MC_SEQ_PMG_CMD_MRS1_LP 2889 drivers/gpu/drm/radeon/ni_dpm.c 	WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
MC_SEQ_PMG_CMD_MRS1_LP 5407 drivers/gpu/drm/radeon/si_dpm.c 			table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
MC_SEQ_PMG_CMD_MRS1_LP 5462 drivers/gpu/drm/radeon/si_dpm.c 		*out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
MC_SEQ_PMG_CMD_MRS1_LP 5551 drivers/gpu/drm/radeon/si_dpm.c 	WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));