MC_SEQ_MISC_TIMING_LP 5892 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		*out_reg = MC_SEQ_MISC_TIMING_LP;
MC_SEQ_MISC_TIMING_LP 6001 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
MC_SEQ_MISC_TIMING_LP 1868 drivers/gpu/drm/radeon/btc_dpm.c 		*out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
MC_SEQ_MISC_TIMING_LP 2033 drivers/gpu/drm/radeon/btc_dpm.c 	WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
MC_SEQ_MISC_TIMING_LP 4431 drivers/gpu/drm/radeon/ci_dpm.c 		*out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
MC_SEQ_MISC_TIMING_LP 4644 drivers/gpu/drm/radeon/ci_dpm.c 	WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
MC_SEQ_MISC_TIMING_LP  980 drivers/gpu/drm/radeon/cypress_dpm.c 	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2;
MC_SEQ_MISC_TIMING_LP 2780 drivers/gpu/drm/radeon/ni_dpm.c 		*out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
MC_SEQ_MISC_TIMING_LP 2885 drivers/gpu/drm/radeon/ni_dpm.c 	WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
MC_SEQ_MISC_TIMING_LP 5438 drivers/gpu/drm/radeon/si_dpm.c 		*out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
MC_SEQ_MISC_TIMING_LP 5547 drivers/gpu/drm/radeon/si_dpm.c 	WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));