MC_SEQ_MISC_TIMING2_LP 5895 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		*out_reg = MC_SEQ_MISC_TIMING2_LP;
MC_SEQ_MISC_TIMING2_LP 6002 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
MC_SEQ_MISC_TIMING2_LP 1871 drivers/gpu/drm/radeon/btc_dpm.c 		*out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
MC_SEQ_MISC_TIMING2_LP 2034 drivers/gpu/drm/radeon/btc_dpm.c 	WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
MC_SEQ_MISC_TIMING2_LP 4434 drivers/gpu/drm/radeon/ci_dpm.c 		*out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
MC_SEQ_MISC_TIMING2_LP 4645 drivers/gpu/drm/radeon/ci_dpm.c 	WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
MC_SEQ_MISC_TIMING2_LP  984 drivers/gpu/drm/radeon/cypress_dpm.c 	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2;
MC_SEQ_MISC_TIMING2_LP 2783 drivers/gpu/drm/radeon/ni_dpm.c 		*out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
MC_SEQ_MISC_TIMING2_LP 2886 drivers/gpu/drm/radeon/ni_dpm.c 	WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
MC_SEQ_MISC_TIMING2_LP 5441 drivers/gpu/drm/radeon/si_dpm.c 		*out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
MC_SEQ_MISC_TIMING2_LP 5548 drivers/gpu/drm/radeon/si_dpm.c 	WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));