MC_SEQ_MISC_TIMING2 5894 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	case MC_SEQ_MISC_TIMING2:
MC_SEQ_MISC_TIMING2 6002 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
MC_SEQ_MISC_TIMING2 1870 drivers/gpu/drm/radeon/btc_dpm.c 	case MC_SEQ_MISC_TIMING2 >> 2:
MC_SEQ_MISC_TIMING2 2034 drivers/gpu/drm/radeon/btc_dpm.c 	WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
MC_SEQ_MISC_TIMING2 4433 drivers/gpu/drm/radeon/ci_dpm.c 	case MC_SEQ_MISC_TIMING2 >> 2:
MC_SEQ_MISC_TIMING2 4645 drivers/gpu/drm/radeon/ci_dpm.c 	WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
MC_SEQ_MISC_TIMING2  985 drivers/gpu/drm/radeon/cypress_dpm.c 	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING2 >> 2;
MC_SEQ_MISC_TIMING2 2782 drivers/gpu/drm/radeon/ni_dpm.c 	case MC_SEQ_MISC_TIMING2 >> 2:
MC_SEQ_MISC_TIMING2 2886 drivers/gpu/drm/radeon/ni_dpm.c 	WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
MC_SEQ_MISC_TIMING2 5440 drivers/gpu/drm/radeon/si_dpm.c 	case MC_SEQ_MISC_TIMING2 >> 2:
MC_SEQ_MISC_TIMING2 5548 drivers/gpu/drm/radeon/si_dpm.c 	WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));