MC_SEQ_MISC_TIMING 5891 drivers/gpu/drm/amd/amdgpu/si_dpm.c case MC_SEQ_MISC_TIMING: MC_SEQ_MISC_TIMING 6001 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); MC_SEQ_MISC_TIMING 1867 drivers/gpu/drm/radeon/btc_dpm.c case MC_SEQ_MISC_TIMING >> 2: MC_SEQ_MISC_TIMING 2033 drivers/gpu/drm/radeon/btc_dpm.c WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); MC_SEQ_MISC_TIMING 4430 drivers/gpu/drm/radeon/ci_dpm.c case MC_SEQ_MISC_TIMING >> 2: MC_SEQ_MISC_TIMING 4597 drivers/gpu/drm/radeon/ci_dpm.c case MC_SEQ_MISC_TIMING: MC_SEQ_MISC_TIMING 4644 drivers/gpu/drm/radeon/ci_dpm.c WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); MC_SEQ_MISC_TIMING 981 drivers/gpu/drm/radeon/cypress_dpm.c eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING >> 2; MC_SEQ_MISC_TIMING 2779 drivers/gpu/drm/radeon/ni_dpm.c case MC_SEQ_MISC_TIMING >> 2: MC_SEQ_MISC_TIMING 2885 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); MC_SEQ_MISC_TIMING 5437 drivers/gpu/drm/radeon/si_dpm.c case MC_SEQ_MISC_TIMING >> 2: MC_SEQ_MISC_TIMING 5547 drivers/gpu/drm/radeon/si_dpm.c WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));