MC_SEQ_CAS_TIMING_LP 5889 drivers/gpu/drm/amd/amdgpu/si_dpm.c 		*out_reg = MC_SEQ_CAS_TIMING_LP;
MC_SEQ_CAS_TIMING_LP 6000 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
MC_SEQ_CAS_TIMING_LP 1865 drivers/gpu/drm/radeon/btc_dpm.c 		*out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
MC_SEQ_CAS_TIMING_LP 2032 drivers/gpu/drm/radeon/btc_dpm.c 	WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
MC_SEQ_CAS_TIMING_LP 4428 drivers/gpu/drm/radeon/ci_dpm.c 		*out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
MC_SEQ_CAS_TIMING_LP 4637 drivers/gpu/drm/radeon/ci_dpm.c 	WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
MC_SEQ_CAS_TIMING_LP  976 drivers/gpu/drm/radeon/cypress_dpm.c 	eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_CAS_TIMING_LP >> 2;
MC_SEQ_CAS_TIMING_LP 2777 drivers/gpu/drm/radeon/ni_dpm.c 		*out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
MC_SEQ_CAS_TIMING_LP 2884 drivers/gpu/drm/radeon/ni_dpm.c 	WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
MC_SEQ_CAS_TIMING_LP 5435 drivers/gpu/drm/radeon/si_dpm.c 		*out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
MC_SEQ_CAS_TIMING_LP 5546 drivers/gpu/drm/radeon/si_dpm.c 	WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));