MC_SEQ_CAS_TIMING 5888 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	case MC_SEQ_CAS_TIMING:
MC_SEQ_CAS_TIMING 6000 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
MC_SEQ_CAS_TIMING 1864 drivers/gpu/drm/radeon/btc_dpm.c 	case MC_SEQ_CAS_TIMING >> 2:
MC_SEQ_CAS_TIMING 2032 drivers/gpu/drm/radeon/btc_dpm.c 	WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
MC_SEQ_CAS_TIMING 4427 drivers/gpu/drm/radeon/ci_dpm.c 	case MC_SEQ_CAS_TIMING >> 2:
MC_SEQ_CAS_TIMING 4585 drivers/gpu/drm/radeon/ci_dpm.c 			case MC_SEQ_CAS_TIMING:
MC_SEQ_CAS_TIMING 4637 drivers/gpu/drm/radeon/ci_dpm.c 	WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
MC_SEQ_CAS_TIMING  977 drivers/gpu/drm/radeon/cypress_dpm.c 	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_CAS_TIMING >> 2;
MC_SEQ_CAS_TIMING 2776 drivers/gpu/drm/radeon/ni_dpm.c 	case MC_SEQ_CAS_TIMING >> 2:
MC_SEQ_CAS_TIMING 2884 drivers/gpu/drm/radeon/ni_dpm.c 	WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
MC_SEQ_CAS_TIMING 5434 drivers/gpu/drm/radeon/si_dpm.c 	case MC_SEQ_CAS_TIMING >> 2:
MC_SEQ_CAS_TIMING 5546 drivers/gpu/drm/radeon/si_dpm.c 	WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));