MC_PMG_CMD_MRS1  5862 drivers/gpu/drm/amd/amdgpu/si_dpm.c 			temp_reg = RREG32(MC_PMG_CMD_MRS1);
MC_PMG_CMD_MRS1  5863 drivers/gpu/drm/amd/amdgpu/si_dpm.c 			table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
MC_PMG_CMD_MRS1  5915 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	case MC_PMG_CMD_MRS1:
MC_PMG_CMD_MRS1  6005 drivers/gpu/drm/amd/amdgpu/si_dpm.c 	WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
MC_PMG_CMD_MRS1  1891 drivers/gpu/drm/radeon/btc_dpm.c 	case MC_PMG_CMD_MRS1 >> 2:
MC_PMG_CMD_MRS1  1956 drivers/gpu/drm/radeon/btc_dpm.c 			tmp = RREG32(MC_PMG_CMD_MRS1);
MC_PMG_CMD_MRS1  1957 drivers/gpu/drm/radeon/btc_dpm.c 			table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
MC_PMG_CMD_MRS1  2041 drivers/gpu/drm/radeon/btc_dpm.c 	WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
MC_PMG_CMD_MRS1  4385 drivers/gpu/drm/radeon/ci_dpm.c 			temp_reg = RREG32(MC_PMG_CMD_MRS1);
MC_PMG_CMD_MRS1  4386 drivers/gpu/drm/radeon/ci_dpm.c 			table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
MC_PMG_CMD_MRS1  4460 drivers/gpu/drm/radeon/ci_dpm.c 	case MC_PMG_CMD_MRS1 >> 2:
MC_PMG_CMD_MRS1  4648 drivers/gpu/drm/radeon/ci_dpm.c 	WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
MC_PMG_CMD_MRS1  1013 drivers/gpu/drm/radeon/cypress_dpm.c 	eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS1 >> 2;
MC_PMG_CMD_MRS1  2747 drivers/gpu/drm/radeon/ni_dpm.c 			temp_reg = RREG32(MC_PMG_CMD_MRS1);
MC_PMG_CMD_MRS1  2748 drivers/gpu/drm/radeon/ni_dpm.c 			table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
MC_PMG_CMD_MRS1  2803 drivers/gpu/drm/radeon/ni_dpm.c 	case MC_PMG_CMD_MRS1 >> 2:
MC_PMG_CMD_MRS1  2889 drivers/gpu/drm/radeon/ni_dpm.c 	WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
MC_PMG_CMD_MRS1  5405 drivers/gpu/drm/radeon/si_dpm.c 			temp_reg = RREG32(MC_PMG_CMD_MRS1);
MC_PMG_CMD_MRS1  5406 drivers/gpu/drm/radeon/si_dpm.c 			table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
MC_PMG_CMD_MRS1  5461 drivers/gpu/drm/radeon/si_dpm.c 	case MC_PMG_CMD_MRS1 >> 2:
MC_PMG_CMD_MRS1  5551 drivers/gpu/drm/radeon/si_dpm.c 	WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));