MCHBAR_MIRROR_BASE_SNB 3329 drivers/gpu/drm/i915/gvt/handlers.c {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL}, MCHBAR_MIRROR_BASE_SNB 3595 drivers/gpu/drm/i915/i915_reg.h #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) MCHBAR_MIRROR_BASE_SNB 3617 drivers/gpu/drm/i915/i915_reg.h #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004) MCHBAR_MIRROR_BASE_SNB 3618 drivers/gpu/drm/i915/i915_reg.h #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008) MCHBAR_MIRROR_BASE_SNB 3619 drivers/gpu/drm/i915/i915_reg.h #define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) MCHBAR_MIRROR_BASE_SNB 3639 drivers/gpu/drm/i915/i915_reg.h #define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10) MCHBAR_MIRROR_BASE_SNB 3643 drivers/gpu/drm/i915/i915_reg.h #define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c) MCHBAR_MIRROR_BASE_SNB 3898 drivers/gpu/drm/i915/i915_reg.h #define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948) MCHBAR_MIRROR_BASE_SNB 3899 drivers/gpu/drm/i915/i915_reg.h #define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070) MCHBAR_MIRROR_BASE_SNB 3900 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994) MCHBAR_MIRROR_BASE_SNB 3901 drivers/gpu/drm/i915/i915_reg.h #define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998) MCHBAR_MIRROR_BASE_SNB 10008 drivers/gpu/drm/i915/i915_reg.h #define BXT_P_CR_MC_BIOS_REQ_0_0_0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114) MCHBAR_MIRROR_BASE_SNB 10018 drivers/gpu/drm/i915/i915_reg.h #define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \ MCHBAR_MIRROR_BASE_SNB 10045 drivers/gpu/drm/i915/i915_reg.h #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04) MCHBAR_MIRROR_BASE_SNB 10048 drivers/gpu/drm/i915/i915_reg.h #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000) MCHBAR_MIRROR_BASE_SNB 10055 drivers/gpu/drm/i915/i915_reg.h #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) MCHBAR_MIRROR_BASE_SNB 10056 drivers/gpu/drm/i915/i915_reg.h #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010) MCHBAR_MIRROR_BASE_SNB 10084 drivers/gpu/drm/i915/i915_reg.h #define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)