MCF_MBAR2          80 arch/m68k/include/asm/m525xsim.h #define MCFINTC2_INTBASE	(MCF_MBAR2 + 0x168)	/* Base Vector Reg */
MCF_MBAR2          81 arch/m68k/include/asm/m525xsim.h #define MCFINTC2_INTPRI1	(MCF_MBAR2 + 0x140)	/* 0-7 priority */
MCF_MBAR2          82 arch/m68k/include/asm/m525xsim.h #define MCFINTC2_INTPRI2	(MCF_MBAR2 + 0x144)	/* 8-15 priority */
MCF_MBAR2          83 arch/m68k/include/asm/m525xsim.h #define MCFINTC2_INTPRI3	(MCF_MBAR2 + 0x148)	/* 16-23 priority */
MCF_MBAR2          84 arch/m68k/include/asm/m525xsim.h #define MCFINTC2_INTPRI4	(MCF_MBAR2 + 0x14c)	/* 24-31 priority */
MCF_MBAR2          85 arch/m68k/include/asm/m525xsim.h #define MCFINTC2_INTPRI5	(MCF_MBAR2 + 0x150)	/* 32-39 priority */
MCF_MBAR2          86 arch/m68k/include/asm/m525xsim.h #define MCFINTC2_INTPRI6	(MCF_MBAR2 + 0x154)	/* 40-47 priority */
MCF_MBAR2          87 arch/m68k/include/asm/m525xsim.h #define MCFINTC2_INTPRI7	(MCF_MBAR2 + 0x158)	/* 48-55 priority */
MCF_MBAR2          88 arch/m68k/include/asm/m525xsim.h #define MCFINTC2_INTPRI8	(MCF_MBAR2 + 0x15c)	/* 56-63 priority */
MCF_MBAR2         130 arch/m68k/include/asm/m525xsim.h #define MCFI2C_BASE1		(MCF_MBAR2 + 0x440)	/* Base address I2C1 */
MCF_MBAR2         189 arch/m68k/include/asm/m525xsim.h #define MCFSIM2_GPIOREAD	(MCF_MBAR2 + 0x000)	/* GPIO read values */
MCF_MBAR2         190 arch/m68k/include/asm/m525xsim.h #define MCFSIM2_GPIOWRITE	(MCF_MBAR2 + 0x004)	/* GPIO write values */
MCF_MBAR2         191 arch/m68k/include/asm/m525xsim.h #define MCFSIM2_GPIOENABLE	(MCF_MBAR2 + 0x008)	/* GPIO enabled */
MCF_MBAR2         192 arch/m68k/include/asm/m525xsim.h #define MCFSIM2_GPIOFUNC	(MCF_MBAR2 + 0x00C)	/* GPIO function */
MCF_MBAR2         193 arch/m68k/include/asm/m525xsim.h #define MCFSIM2_GPIO1READ	(MCF_MBAR2 + 0x0B0)	/* GPIO1 read values */
MCF_MBAR2         194 arch/m68k/include/asm/m525xsim.h #define MCFSIM2_GPIO1WRITE	(MCF_MBAR2 + 0x0B4)	/* GPIO1 write values */
MCF_MBAR2         195 arch/m68k/include/asm/m525xsim.h #define MCFSIM2_GPIO1ENABLE	(MCF_MBAR2 + 0x0B8)	/* GPIO1 enabled */
MCF_MBAR2         196 arch/m68k/include/asm/m525xsim.h #define MCFSIM2_GPIO1FUNC	(MCF_MBAR2 + 0x0BC)	/* GPIO1 function */
MCF_MBAR2         198 arch/m68k/include/asm/m525xsim.h #define MCFSIM2_GPIOINTSTAT	(MCF_MBAR2 + 0xc0)	/* GPIO intr status */
MCF_MBAR2         199 arch/m68k/include/asm/m525xsim.h #define MCFSIM2_GPIOINTCLEAR	(MCF_MBAR2 + 0xc0)	/* GPIO intr clear */
MCF_MBAR2         200 arch/m68k/include/asm/m525xsim.h #define MCFSIM2_GPIOINTENABLE	(MCF_MBAR2 + 0xc4)	/* GPIO intr enable */
MCF_MBAR2         202 arch/m68k/include/asm/m525xsim.h #define MCFSIM2_DMAROUTE	(MCF_MBAR2 + 0x188)     /* DMA routing */
MCF_MBAR2         203 arch/m68k/include/asm/m525xsim.h #define MCFSIM2_IDECONFIG1	(MCF_MBAR2 + 0x18c)	/* IDEconfig1 */
MCF_MBAR2         204 arch/m68k/include/asm/m525xsim.h #define MCFSIM2_IDECONFIG2	(MCF_MBAR2 + 0x190)	/* IDEconfig2 */