MCF_MBAR 25 arch/m68k/include/asm/m5206sim.h #define MCFSIM_SIMR (MCF_MBAR + 0x03) /* SIM Config reg */ MCF_MBAR 26 arch/m68k/include/asm/m5206sim.h #define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */ MCF_MBAR 27 arch/m68k/include/asm/m5206sim.h #define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */ MCF_MBAR 28 arch/m68k/include/asm/m5206sim.h #define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */ MCF_MBAR 29 arch/m68k/include/asm/m5206sim.h #define MCFSIM_ICR4 (MCF_MBAR + 0x17) /* Intr Ctrl reg 4 */ MCF_MBAR 30 arch/m68k/include/asm/m5206sim.h #define MCFSIM_ICR5 (MCF_MBAR + 0x18) /* Intr Ctrl reg 5 */ MCF_MBAR 31 arch/m68k/include/asm/m5206sim.h #define MCFSIM_ICR6 (MCF_MBAR + 0x19) /* Intr Ctrl reg 6 */ MCF_MBAR 32 arch/m68k/include/asm/m5206sim.h #define MCFSIM_ICR7 (MCF_MBAR + 0x1a) /* Intr Ctrl reg 7 */ MCF_MBAR 33 arch/m68k/include/asm/m5206sim.h #define MCFSIM_ICR8 (MCF_MBAR + 0x1b) /* Intr Ctrl reg 8 */ MCF_MBAR 34 arch/m68k/include/asm/m5206sim.h #define MCFSIM_ICR9 (MCF_MBAR + 0x1c) /* Intr Ctrl reg 9 */ MCF_MBAR 35 arch/m68k/include/asm/m5206sim.h #define MCFSIM_ICR10 (MCF_MBAR + 0x1d) /* Intr Ctrl reg 10 */ MCF_MBAR 36 arch/m68k/include/asm/m5206sim.h #define MCFSIM_ICR11 (MCF_MBAR + 0x1e) /* Intr Ctrl reg 11 */ MCF_MBAR 37 arch/m68k/include/asm/m5206sim.h #define MCFSIM_ICR12 (MCF_MBAR + 0x1f) /* Intr Ctrl reg 12 */ MCF_MBAR 38 arch/m68k/include/asm/m5206sim.h #define MCFSIM_ICR13 (MCF_MBAR + 0x20) /* Intr Ctrl reg 13 */ MCF_MBAR 40 arch/m68k/include/asm/m5206sim.h #define MCFSIM_ICR14 (MCF_MBAR + 0x21) /* Intr Ctrl reg 14 */ MCF_MBAR 41 arch/m68k/include/asm/m5206sim.h #define MCFSIM_ICR15 (MCF_MBAR + 0x22) /* Intr Ctrl reg 15 */ MCF_MBAR 44 arch/m68k/include/asm/m5206sim.h #define MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */ MCF_MBAR 45 arch/m68k/include/asm/m5206sim.h #define MCFSIM_IPR (MCF_MBAR + 0x3a) /* Interrupt Pending */ MCF_MBAR 47 arch/m68k/include/asm/m5206sim.h #define MCFSIM_RSR (MCF_MBAR + 0x40) /* Reset Status */ MCF_MBAR 48 arch/m68k/include/asm/m5206sim.h #define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */ MCF_MBAR 50 arch/m68k/include/asm/m5206sim.h #define MCFSIM_SWIVR (MCF_MBAR + 0x42) /* SW Watchdog intr */ MCF_MBAR 51 arch/m68k/include/asm/m5206sim.h #define MCFSIM_SWSR (MCF_MBAR + 0x43) /* SW Watchdog srv */ MCF_MBAR 53 arch/m68k/include/asm/m5206sim.h #define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */ MCF_MBAR 54 arch/m68k/include/asm/m5206sim.h #define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */ MCF_MBAR 55 arch/m68k/include/asm/m5206sim.h #define MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */ MCF_MBAR 56 arch/m68k/include/asm/m5206sim.h #define MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */ MCF_MBAR 57 arch/m68k/include/asm/m5206sim.h #define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */ MCF_MBAR 58 arch/m68k/include/asm/m5206sim.h #define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */ MCF_MBAR 59 arch/m68k/include/asm/m5206sim.h #define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */ MCF_MBAR 60 arch/m68k/include/asm/m5206sim.h #define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */ MCF_MBAR 62 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */ MCF_MBAR 63 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */ MCF_MBAR 64 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */ MCF_MBAR 65 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */ MCF_MBAR 66 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */ MCF_MBAR 67 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */ MCF_MBAR 68 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSAR2 (MCF_MBAR + 0x7c) /* CS 2 Address reg */ MCF_MBAR 69 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSMR2 (MCF_MBAR + 0x80) /* CS 2 Mask reg */ MCF_MBAR 70 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSCR2 (MCF_MBAR + 0x86) /* CS 2 Control reg */ MCF_MBAR 71 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSAR3 (MCF_MBAR + 0x88) /* CS 3 Address reg */ MCF_MBAR 72 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSMR3 (MCF_MBAR + 0x8c) /* CS 3 Mask reg */ MCF_MBAR 73 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSCR3 (MCF_MBAR + 0x92) /* CS 3 Control reg */ MCF_MBAR 74 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSAR4 (MCF_MBAR + 0x94) /* CS 4 Address reg */ MCF_MBAR 75 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSMR4 (MCF_MBAR + 0x98) /* CS 4 Mask reg */ MCF_MBAR 76 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSCR4 (MCF_MBAR + 0x9e) /* CS 4 Control reg */ MCF_MBAR 77 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSAR5 (MCF_MBAR + 0xa0) /* CS 5 Address reg */ MCF_MBAR 78 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSMR5 (MCF_MBAR + 0xa4) /* CS 5 Mask reg */ MCF_MBAR 79 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSCR5 (MCF_MBAR + 0xaa) /* CS 5 Control reg */ MCF_MBAR 80 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSAR6 (MCF_MBAR + 0xac) /* CS 6 Address reg */ MCF_MBAR 81 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSMR6 (MCF_MBAR + 0xb0) /* CS 6 Mask reg */ MCF_MBAR 82 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSCR6 (MCF_MBAR + 0xb6) /* CS 6 Control reg */ MCF_MBAR 83 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSAR7 (MCF_MBAR + 0xb8) /* CS 7 Address reg */ MCF_MBAR 84 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSMR7 (MCF_MBAR + 0xbc) /* CS 7 Mask reg */ MCF_MBAR 85 arch/m68k/include/asm/m5206sim.h #define MCFSIM_CSCR7 (MCF_MBAR + 0xc2) /* CS 7 Control reg */ MCF_MBAR 86 arch/m68k/include/asm/m5206sim.h #define MCFSIM_DMCR (MCF_MBAR + 0xc6) /* Default control */ MCF_MBAR 89 arch/m68k/include/asm/m5206sim.h #define MCFSIM_PAR (MCF_MBAR + 0xca) /* Pin Assignment */ MCF_MBAR 91 arch/m68k/include/asm/m5206sim.h #define MCFSIM_PAR (MCF_MBAR + 0xcb) /* Pin Assignment */ MCF_MBAR 94 arch/m68k/include/asm/m5206sim.h #define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */ MCF_MBAR 95 arch/m68k/include/asm/m5206sim.h #define MCFTIMER_BASE2 (MCF_MBAR + 0x120) /* Base of TIMER2 */ MCF_MBAR 97 arch/m68k/include/asm/m5206sim.h #define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */ MCF_MBAR 98 arch/m68k/include/asm/m5206sim.h #define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */ MCF_MBAR 100 arch/m68k/include/asm/m5206sim.h #define MCFDMA_BASE0 (MCF_MBAR + 0x200) /* Base address DMA 0 */ MCF_MBAR 101 arch/m68k/include/asm/m5206sim.h #define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */ MCF_MBAR 104 arch/m68k/include/asm/m5206sim.h #define MCFUART_BASE0 (MCF_MBAR + 0x180) /* Base address UART0 */ MCF_MBAR 105 arch/m68k/include/asm/m5206sim.h #define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */ MCF_MBAR 107 arch/m68k/include/asm/m5206sim.h #define MCFUART_BASE0 (MCF_MBAR + 0x140) /* Base address UART0 */ MCF_MBAR 108 arch/m68k/include/asm/m5206sim.h #define MCFUART_BASE1 (MCF_MBAR + 0x180) /* Base address UART1 */ MCF_MBAR 154 arch/m68k/include/asm/m5206sim.h #define MCFI2C_BASE0 (MCF_MBAR + 0x1e0) MCF_MBAR 35 arch/m68k/include/asm/m525xsim.h #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */ MCF_MBAR 36 arch/m68k/include/asm/m525xsim.h #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ MCF_MBAR 37 arch/m68k/include/asm/m525xsim.h #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ MCF_MBAR 38 arch/m68k/include/asm/m525xsim.h #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */ MCF_MBAR 39 arch/m68k/include/asm/m525xsim.h #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */ MCF_MBAR 40 arch/m68k/include/asm/m525xsim.h #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */ MCF_MBAR 41 arch/m68k/include/asm/m525xsim.h #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */ MCF_MBAR 42 arch/m68k/include/asm/m525xsim.h #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */ MCF_MBAR 43 arch/m68k/include/asm/m525xsim.h #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */ MCF_MBAR 44 arch/m68k/include/asm/m525xsim.h #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */ MCF_MBAR 45 arch/m68k/include/asm/m525xsim.h #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */ MCF_MBAR 46 arch/m68k/include/asm/m525xsim.h #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */ MCF_MBAR 47 arch/m68k/include/asm/m525xsim.h #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */ MCF_MBAR 48 arch/m68k/include/asm/m525xsim.h #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */ MCF_MBAR 49 arch/m68k/include/asm/m525xsim.h #define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */ MCF_MBAR 50 arch/m68k/include/asm/m525xsim.h #define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */ MCF_MBAR 51 arch/m68k/include/asm/m525xsim.h #define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */ MCF_MBAR 52 arch/m68k/include/asm/m525xsim.h #define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */ MCF_MBAR 53 arch/m68k/include/asm/m525xsim.h #define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */ MCF_MBAR 55 arch/m68k/include/asm/m525xsim.h #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */ MCF_MBAR 56 arch/m68k/include/asm/m525xsim.h #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */ MCF_MBAR 57 arch/m68k/include/asm/m525xsim.h #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */ MCF_MBAR 58 arch/m68k/include/asm/m525xsim.h #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */ MCF_MBAR 59 arch/m68k/include/asm/m525xsim.h #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */ MCF_MBAR 60 arch/m68k/include/asm/m525xsim.h #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */ MCF_MBAR 61 arch/m68k/include/asm/m525xsim.h #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */ MCF_MBAR 62 arch/m68k/include/asm/m525xsim.h #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */ MCF_MBAR 63 arch/m68k/include/asm/m525xsim.h #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */ MCF_MBAR 64 arch/m68k/include/asm/m525xsim.h #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */ MCF_MBAR 65 arch/m68k/include/asm/m525xsim.h #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */ MCF_MBAR 66 arch/m68k/include/asm/m525xsim.h #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */ MCF_MBAR 67 arch/m68k/include/asm/m525xsim.h #define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */ MCF_MBAR 68 arch/m68k/include/asm/m525xsim.h #define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */ MCF_MBAR 69 arch/m68k/include/asm/m525xsim.h #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */ MCF_MBAR 71 arch/m68k/include/asm/m525xsim.h #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ MCF_MBAR 72 arch/m68k/include/asm/m525xsim.h #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ MCF_MBAR 73 arch/m68k/include/asm/m525xsim.h #define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */ MCF_MBAR 74 arch/m68k/include/asm/m525xsim.h #define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */ MCF_MBAR 75 arch/m68k/include/asm/m525xsim.h #define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */ MCF_MBAR 97 arch/m68k/include/asm/m525xsim.h #define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ MCF_MBAR 98 arch/m68k/include/asm/m525xsim.h #define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ MCF_MBAR 103 arch/m68k/include/asm/m525xsim.h #define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */ MCF_MBAR 104 arch/m68k/include/asm/m525xsim.h #define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */ MCF_MBAR 109 arch/m68k/include/asm/m525xsim.h #define MCFQSPI_BASE (MCF_MBAR + 0x400) /* Base address QSPI */ MCF_MBAR 127 arch/m68k/include/asm/m525xsim.h #define MCFI2C_BASE0 (MCF_MBAR + 0x280) /* Base address I2C0 */ MCF_MBAR 136 arch/m68k/include/asm/m525xsim.h #define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */ MCF_MBAR 137 arch/m68k/include/asm/m525xsim.h #define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */ MCF_MBAR 138 arch/m68k/include/asm/m525xsim.h #define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */ MCF_MBAR 139 arch/m68k/include/asm/m525xsim.h #define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */ MCF_MBAR 25 arch/m68k/include/asm/m5272sim.h #define MCFSIM_SCR (MCF_MBAR + 0x04) /* SIM Config reg */ MCF_MBAR 26 arch/m68k/include/asm/m5272sim.h #define MCFSIM_SPR (MCF_MBAR + 0x06) /* System Protection */ MCF_MBAR 27 arch/m68k/include/asm/m5272sim.h #define MCFSIM_PMR (MCF_MBAR + 0x08) /* Power Management */ MCF_MBAR 28 arch/m68k/include/asm/m5272sim.h #define MCFSIM_APMR (MCF_MBAR + 0x0e) /* Active Low Power */ MCF_MBAR 29 arch/m68k/include/asm/m5272sim.h #define MCFSIM_DIR (MCF_MBAR + 0x10) /* Device Identity */ MCF_MBAR 31 arch/m68k/include/asm/m5272sim.h #define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */ MCF_MBAR 32 arch/m68k/include/asm/m5272sim.h #define MCFSIM_ICR2 (MCF_MBAR + 0x24) /* Intr Ctrl reg 2 */ MCF_MBAR 33 arch/m68k/include/asm/m5272sim.h #define MCFSIM_ICR3 (MCF_MBAR + 0x28) /* Intr Ctrl reg 3 */ MCF_MBAR 34 arch/m68k/include/asm/m5272sim.h #define MCFSIM_ICR4 (MCF_MBAR + 0x2c) /* Intr Ctrl reg 4 */ MCF_MBAR 36 arch/m68k/include/asm/m5272sim.h #define MCFSIM_ISR (MCF_MBAR + 0x30) /* Intr Source */ MCF_MBAR 37 arch/m68k/include/asm/m5272sim.h #define MCFSIM_PITR (MCF_MBAR + 0x34) /* Intr Transition */ MCF_MBAR 38 arch/m68k/include/asm/m5272sim.h #define MCFSIM_PIWR (MCF_MBAR + 0x38) /* Intr Wakeup */ MCF_MBAR 39 arch/m68k/include/asm/m5272sim.h #define MCFSIM_PIVR (MCF_MBAR + 0x3f) /* Intr Vector */ MCF_MBAR 41 arch/m68k/include/asm/m5272sim.h #define MCFSIM_WRRR (MCF_MBAR + 0x280) /* Watchdog reference */ MCF_MBAR 42 arch/m68k/include/asm/m5272sim.h #define MCFSIM_WIRR (MCF_MBAR + 0x284) /* Watchdog interrupt */ MCF_MBAR 43 arch/m68k/include/asm/m5272sim.h #define MCFSIM_WCR (MCF_MBAR + 0x288) /* Watchdog counter */ MCF_MBAR 44 arch/m68k/include/asm/m5272sim.h #define MCFSIM_WER (MCF_MBAR + 0x28c) /* Watchdog event */ MCF_MBAR 46 arch/m68k/include/asm/m5272sim.h #define MCFSIM_CSBR0 (MCF_MBAR + 0x40) /* CS0 Base Address */ MCF_MBAR 47 arch/m68k/include/asm/m5272sim.h #define MCFSIM_CSOR0 (MCF_MBAR + 0x44) /* CS0 Option */ MCF_MBAR 48 arch/m68k/include/asm/m5272sim.h #define MCFSIM_CSBR1 (MCF_MBAR + 0x48) /* CS1 Base Address */ MCF_MBAR 49 arch/m68k/include/asm/m5272sim.h #define MCFSIM_CSOR1 (MCF_MBAR + 0x4c) /* CS1 Option */ MCF_MBAR 50 arch/m68k/include/asm/m5272sim.h #define MCFSIM_CSBR2 (MCF_MBAR + 0x50) /* CS2 Base Address */ MCF_MBAR 51 arch/m68k/include/asm/m5272sim.h #define MCFSIM_CSOR2 (MCF_MBAR + 0x54) /* CS2 Option */ MCF_MBAR 52 arch/m68k/include/asm/m5272sim.h #define MCFSIM_CSBR3 (MCF_MBAR + 0x58) /* CS3 Base Address */ MCF_MBAR 53 arch/m68k/include/asm/m5272sim.h #define MCFSIM_CSOR3 (MCF_MBAR + 0x5c) /* CS3 Option */ MCF_MBAR 54 arch/m68k/include/asm/m5272sim.h #define MCFSIM_CSBR4 (MCF_MBAR + 0x60) /* CS4 Base Address */ MCF_MBAR 55 arch/m68k/include/asm/m5272sim.h #define MCFSIM_CSOR4 (MCF_MBAR + 0x64) /* CS4 Option */ MCF_MBAR 56 arch/m68k/include/asm/m5272sim.h #define MCFSIM_CSBR5 (MCF_MBAR + 0x68) /* CS5 Base Address */ MCF_MBAR 57 arch/m68k/include/asm/m5272sim.h #define MCFSIM_CSOR5 (MCF_MBAR + 0x6c) /* CS5 Option */ MCF_MBAR 58 arch/m68k/include/asm/m5272sim.h #define MCFSIM_CSBR6 (MCF_MBAR + 0x70) /* CS6 Base Address */ MCF_MBAR 59 arch/m68k/include/asm/m5272sim.h #define MCFSIM_CSOR6 (MCF_MBAR + 0x74) /* CS6 Option */ MCF_MBAR 60 arch/m68k/include/asm/m5272sim.h #define MCFSIM_CSBR7 (MCF_MBAR + 0x78) /* CS7 Base Address */ MCF_MBAR 61 arch/m68k/include/asm/m5272sim.h #define MCFSIM_CSOR7 (MCF_MBAR + 0x7c) /* CS7 Option */ MCF_MBAR 63 arch/m68k/include/asm/m5272sim.h #define MCFSIM_SDCR (MCF_MBAR + 0x180) /* SDRAM Config */ MCF_MBAR 64 arch/m68k/include/asm/m5272sim.h #define MCFSIM_SDTR (MCF_MBAR + 0x184) /* SDRAM Timing */ MCF_MBAR 65 arch/m68k/include/asm/m5272sim.h #define MCFSIM_DCAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address */ MCF_MBAR 66 arch/m68k/include/asm/m5272sim.h #define MCFSIM_DCMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask */ MCF_MBAR 67 arch/m68k/include/asm/m5272sim.h #define MCFSIM_DCCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control */ MCF_MBAR 68 arch/m68k/include/asm/m5272sim.h #define MCFSIM_DCAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address */ MCF_MBAR 69 arch/m68k/include/asm/m5272sim.h #define MCFSIM_DCMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg */ MCF_MBAR 70 arch/m68k/include/asm/m5272sim.h #define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */ MCF_MBAR 72 arch/m68k/include/asm/m5272sim.h #define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */ MCF_MBAR 73 arch/m68k/include/asm/m5272sim.h #define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */ MCF_MBAR 75 arch/m68k/include/asm/m5272sim.h #define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */ MCF_MBAR 76 arch/m68k/include/asm/m5272sim.h #define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */ MCF_MBAR 77 arch/m68k/include/asm/m5272sim.h #define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */ MCF_MBAR 78 arch/m68k/include/asm/m5272sim.h #define MCFSIM_PBCNT (MCF_MBAR + 0x88) /* Port B Control (r/w) */ MCF_MBAR 79 arch/m68k/include/asm/m5272sim.h #define MCFSIM_PBDDR (MCF_MBAR + 0x8c) /* Port B Direction (r/w) */ MCF_MBAR 80 arch/m68k/include/asm/m5272sim.h #define MCFSIM_PBDAT (MCF_MBAR + 0x8e) /* Port B Data (r/w) */ MCF_MBAR 81 arch/m68k/include/asm/m5272sim.h #define MCFSIM_PCDDR (MCF_MBAR + 0x94) /* Port C Direction (r/w) */ MCF_MBAR 82 arch/m68k/include/asm/m5272sim.h #define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */ MCF_MBAR 83 arch/m68k/include/asm/m5272sim.h #define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */ MCF_MBAR 85 arch/m68k/include/asm/m5272sim.h #define MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */ MCF_MBAR 87 arch/m68k/include/asm/m5272sim.h #define MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */ MCF_MBAR 88 arch/m68k/include/asm/m5272sim.h #define MCFTIMER_BASE2 (MCF_MBAR + 0x220) /* Base address TIMER2 */ MCF_MBAR 89 arch/m68k/include/asm/m5272sim.h #define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */ MCF_MBAR 90 arch/m68k/include/asm/m5272sim.h #define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */ MCF_MBAR 92 arch/m68k/include/asm/m5272sim.h #define MCFFEC_BASE0 (MCF_MBAR + 0x840) /* Base FEC ethernet */ MCF_MBAR 27 arch/m68k/include/asm/m5307sim.h #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */ MCF_MBAR 28 arch/m68k/include/asm/m5307sim.h #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ MCF_MBAR 29 arch/m68k/include/asm/m5307sim.h #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ MCF_MBAR 30 arch/m68k/include/asm/m5307sim.h #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/ MCF_MBAR 31 arch/m68k/include/asm/m5307sim.h #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */ MCF_MBAR 32 arch/m68k/include/asm/m5307sim.h #define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Itr Assignment */ MCF_MBAR 33 arch/m68k/include/asm/m5307sim.h #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl Reg */ MCF_MBAR 34 arch/m68k/include/asm/m5307sim.h #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */ MCF_MBAR 35 arch/m68k/include/asm/m5307sim.h #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pend */ MCF_MBAR 36 arch/m68k/include/asm/m5307sim.h #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */ MCF_MBAR 37 arch/m68k/include/asm/m5307sim.h #define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */ MCF_MBAR 38 arch/m68k/include/asm/m5307sim.h #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */ MCF_MBAR 39 arch/m68k/include/asm/m5307sim.h #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */ MCF_MBAR 40 arch/m68k/include/asm/m5307sim.h #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */ MCF_MBAR 41 arch/m68k/include/asm/m5307sim.h #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */ MCF_MBAR 42 arch/m68k/include/asm/m5307sim.h #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */ MCF_MBAR 43 arch/m68k/include/asm/m5307sim.h #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */ MCF_MBAR 44 arch/m68k/include/asm/m5307sim.h #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */ MCF_MBAR 45 arch/m68k/include/asm/m5307sim.h #define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */ MCF_MBAR 46 arch/m68k/include/asm/m5307sim.h #define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */ MCF_MBAR 47 arch/m68k/include/asm/m5307sim.h #define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */ MCF_MBAR 48 arch/m68k/include/asm/m5307sim.h #define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */ MCF_MBAR 49 arch/m68k/include/asm/m5307sim.h #define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */ MCF_MBAR 51 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */ MCF_MBAR 52 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */ MCF_MBAR 53 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */ MCF_MBAR 54 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */ MCF_MBAR 55 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */ MCF_MBAR 56 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */ MCF_MBAR 59 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSBAR (MCF_MBAR + 0x98) /* CS Base Address */ MCF_MBAR 60 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSBAMR (MCF_MBAR + 0x9c) /* CS Base Mask */ MCF_MBAR 61 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSMR2 (MCF_MBAR + 0x9e) /* CS 2 Mask reg */ MCF_MBAR 62 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */ MCF_MBAR 63 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSMR3 (MCF_MBAR + 0xaa) /* CS 3 Mask reg */ MCF_MBAR 64 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */ MCF_MBAR 65 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSMR4 (MCF_MBAR + 0xb6) /* CS 4 Mask reg */ MCF_MBAR 66 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */ MCF_MBAR 67 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSMR5 (MCF_MBAR + 0xc2) /* CS 5 Mask reg */ MCF_MBAR 68 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */ MCF_MBAR 69 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSMR6 (MCF_MBAR + 0xce) /* CS 6 Mask reg */ MCF_MBAR 70 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */ MCF_MBAR 71 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSMR7 (MCF_MBAR + 0xda) /* CS 7 Mask reg */ MCF_MBAR 72 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */ MCF_MBAR 74 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */ MCF_MBAR 75 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */ MCF_MBAR 76 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */ MCF_MBAR 77 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */ MCF_MBAR 78 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */ MCF_MBAR 79 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */ MCF_MBAR 80 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */ MCF_MBAR 81 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */ MCF_MBAR 82 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */ MCF_MBAR 83 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */ MCF_MBAR 84 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */ MCF_MBAR 85 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */ MCF_MBAR 86 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */ MCF_MBAR 87 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */ MCF_MBAR 88 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */ MCF_MBAR 89 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */ MCF_MBAR 90 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */ MCF_MBAR 91 arch/m68k/include/asm/m5307sim.h #define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */ MCF_MBAR 94 arch/m68k/include/asm/m5307sim.h #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ MCF_MBAR 95 arch/m68k/include/asm/m5307sim.h #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM Addr/Ctrl 0 */ MCF_MBAR 96 arch/m68k/include/asm/m5307sim.h #define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM Mask 0 */ MCF_MBAR 97 arch/m68k/include/asm/m5307sim.h #define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM Addr/Ctrl 1 */ MCF_MBAR 98 arch/m68k/include/asm/m5307sim.h #define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM Mask 1 */ MCF_MBAR 103 arch/m68k/include/asm/m5307sim.h #define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ MCF_MBAR 104 arch/m68k/include/asm/m5307sim.h #define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ MCF_MBAR 106 arch/m68k/include/asm/m5307sim.h #define MCFSIM_PADDR (MCF_MBAR + 0x244) MCF_MBAR 107 arch/m68k/include/asm/m5307sim.h #define MCFSIM_PADAT (MCF_MBAR + 0x248) MCF_MBAR 112 arch/m68k/include/asm/m5307sim.h #define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */ MCF_MBAR 113 arch/m68k/include/asm/m5307sim.h #define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */ MCF_MBAR 114 arch/m68k/include/asm/m5307sim.h #define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */ MCF_MBAR 115 arch/m68k/include/asm/m5307sim.h #define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */ MCF_MBAR 121 arch/m68k/include/asm/m5307sim.h #define MCFUART_BASE0 (MCF_MBAR + 0x200) /* Base address UART0 */ MCF_MBAR 122 arch/m68k/include/asm/m5307sim.h #define MCFUART_BASE1 (MCF_MBAR + 0x1c0) /* Base address UART1 */ MCF_MBAR 124 arch/m68k/include/asm/m5307sim.h #define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */ MCF_MBAR 125 arch/m68k/include/asm/m5307sim.h #define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */ MCF_MBAR 187 arch/m68k/include/asm/m5307sim.h #define MCFI2C_BASE0 (MCF_MBAR + 0x280) MCF_MBAR 27 arch/m68k/include/asm/m5407sim.h #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */ MCF_MBAR 28 arch/m68k/include/asm/m5407sim.h #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ MCF_MBAR 29 arch/m68k/include/asm/m5407sim.h #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ MCF_MBAR 30 arch/m68k/include/asm/m5407sim.h #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/ MCF_MBAR 31 arch/m68k/include/asm/m5407sim.h #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */ MCF_MBAR 32 arch/m68k/include/asm/m5407sim.h #define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */ MCF_MBAR 33 arch/m68k/include/asm/m5407sim.h #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl */ MCF_MBAR 34 arch/m68k/include/asm/m5407sim.h #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */ MCF_MBAR 35 arch/m68k/include/asm/m5407sim.h #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */ MCF_MBAR 36 arch/m68k/include/asm/m5407sim.h #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */ MCF_MBAR 37 arch/m68k/include/asm/m5407sim.h #define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */ MCF_MBAR 38 arch/m68k/include/asm/m5407sim.h #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */ MCF_MBAR 39 arch/m68k/include/asm/m5407sim.h #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */ MCF_MBAR 40 arch/m68k/include/asm/m5407sim.h #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */ MCF_MBAR 41 arch/m68k/include/asm/m5407sim.h #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */ MCF_MBAR 42 arch/m68k/include/asm/m5407sim.h #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */ MCF_MBAR 43 arch/m68k/include/asm/m5407sim.h #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */ MCF_MBAR 44 arch/m68k/include/asm/m5407sim.h #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */ MCF_MBAR 45 arch/m68k/include/asm/m5407sim.h #define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */ MCF_MBAR 46 arch/m68k/include/asm/m5407sim.h #define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */ MCF_MBAR 47 arch/m68k/include/asm/m5407sim.h #define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */ MCF_MBAR 48 arch/m68k/include/asm/m5407sim.h #define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */ MCF_MBAR 49 arch/m68k/include/asm/m5407sim.h #define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */ MCF_MBAR 51 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */ MCF_MBAR 52 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */ MCF_MBAR 53 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */ MCF_MBAR 54 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */ MCF_MBAR 55 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */ MCF_MBAR 56 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */ MCF_MBAR 58 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */ MCF_MBAR 59 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */ MCF_MBAR 60 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */ MCF_MBAR 61 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */ MCF_MBAR 62 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */ MCF_MBAR 63 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */ MCF_MBAR 64 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */ MCF_MBAR 65 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */ MCF_MBAR 66 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */ MCF_MBAR 67 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */ MCF_MBAR 68 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */ MCF_MBAR 69 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */ MCF_MBAR 70 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */ MCF_MBAR 71 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */ MCF_MBAR 72 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */ MCF_MBAR 73 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */ MCF_MBAR 74 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */ MCF_MBAR 75 arch/m68k/include/asm/m5407sim.h #define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */ MCF_MBAR 77 arch/m68k/include/asm/m5407sim.h #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ MCF_MBAR 78 arch/m68k/include/asm/m5407sim.h #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ MCF_MBAR 79 arch/m68k/include/asm/m5407sim.h #define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */ MCF_MBAR 80 arch/m68k/include/asm/m5407sim.h #define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */ MCF_MBAR 81 arch/m68k/include/asm/m5407sim.h #define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */ MCF_MBAR 86 arch/m68k/include/asm/m5407sim.h #define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ MCF_MBAR 87 arch/m68k/include/asm/m5407sim.h #define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ MCF_MBAR 89 arch/m68k/include/asm/m5407sim.h #define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */ MCF_MBAR 90 arch/m68k/include/asm/m5407sim.h #define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */ MCF_MBAR 92 arch/m68k/include/asm/m5407sim.h #define MCFSIM_PADDR (MCF_MBAR + 0x244) MCF_MBAR 93 arch/m68k/include/asm/m5407sim.h #define MCFSIM_PADAT (MCF_MBAR + 0x248) MCF_MBAR 98 arch/m68k/include/asm/m5407sim.h #define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */ MCF_MBAR 99 arch/m68k/include/asm/m5407sim.h #define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */ MCF_MBAR 100 arch/m68k/include/asm/m5407sim.h #define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */ MCF_MBAR 101 arch/m68k/include/asm/m5407sim.h #define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */ MCF_MBAR 151 arch/m68k/include/asm/m5407sim.h #define MCFI2C_BASE0 (MCF_MBAR + 0x280) MCF_MBAR 20 arch/m68k/include/asm/m54xxgpt.h #define MCF_GPT_GMS0 (MCF_MBAR + 0x000800) MCF_MBAR 21 arch/m68k/include/asm/m54xxgpt.h #define MCF_GPT_GCIR0 (MCF_MBAR + 0x000804) MCF_MBAR 22 arch/m68k/include/asm/m54xxgpt.h #define MCF_GPT_GPWM0 (MCF_MBAR + 0x000808) MCF_MBAR 23 arch/m68k/include/asm/m54xxgpt.h #define MCF_GPT_GSR0 (MCF_MBAR + 0x00080C) MCF_MBAR 24 arch/m68k/include/asm/m54xxgpt.h #define MCF_GPT_GMS1 (MCF_MBAR + 0x000810) MCF_MBAR 25 arch/m68k/include/asm/m54xxgpt.h #define MCF_GPT_GCIR1 (MCF_MBAR + 0x000814) MCF_MBAR 26 arch/m68k/include/asm/m54xxgpt.h #define MCF_GPT_GPWM1 (MCF_MBAR + 0x000818) MCF_MBAR 27 arch/m68k/include/asm/m54xxgpt.h #define MCF_GPT_GSR1 (MCF_MBAR + 0x00081C) MCF_MBAR 28 arch/m68k/include/asm/m54xxgpt.h #define MCF_GPT_GMS2 (MCF_MBAR + 0x000820) MCF_MBAR 29 arch/m68k/include/asm/m54xxgpt.h #define MCF_GPT_GCIR2 (MCF_MBAR + 0x000824) MCF_MBAR 30 arch/m68k/include/asm/m54xxgpt.h #define MCF_GPT_GPWM2 (MCF_MBAR + 0x000828) MCF_MBAR 31 arch/m68k/include/asm/m54xxgpt.h #define MCF_GPT_GSR2 (MCF_MBAR + 0x00082C) MCF_MBAR 32 arch/m68k/include/asm/m54xxgpt.h #define MCF_GPT_GMS3 (MCF_MBAR + 0x000830) MCF_MBAR 33 arch/m68k/include/asm/m54xxgpt.h #define MCF_GPT_GCIR3 (MCF_MBAR + 0x000834) MCF_MBAR 34 arch/m68k/include/asm/m54xxgpt.h #define MCF_GPT_GPWM3 (MCF_MBAR + 0x000838) MCF_MBAR 35 arch/m68k/include/asm/m54xxgpt.h #define MCF_GPT_GSR3 (MCF_MBAR + 0x00083C) MCF_MBAR 36 arch/m68k/include/asm/m54xxgpt.h #define MCF_GPT_GMS(x) (MCF_MBAR + 0x000800 + ((x) * 0x010)) MCF_MBAR 37 arch/m68k/include/asm/m54xxgpt.h #define MCF_GPT_GCIR(x) (MCF_MBAR + 0x000804 + ((x) * 0x010)) MCF_MBAR 38 arch/m68k/include/asm/m54xxgpt.h #define MCF_GPT_GPWM(x) (MCF_MBAR + 0x000808 + ((x) * 0x010)) MCF_MBAR 39 arch/m68k/include/asm/m54xxgpt.h #define MCF_GPT_GSR(x) (MCF_MBAR + 0x00080C + ((x) * 0x010)) MCF_MBAR 14 arch/m68k/include/asm/m54xxsim.h #define IOMEMBASE MCF_MBAR MCF_MBAR 24 arch/m68k/include/asm/m54xxsim.h #define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */ MCF_MBAR 39 arch/m68k/include/asm/m54xxsim.h #define MCFUART_BASE0 (MCF_MBAR + 0x8600) /* Base address UART0 */ MCF_MBAR 40 arch/m68k/include/asm/m54xxsim.h #define MCFUART_BASE1 (MCF_MBAR + 0x8700) /* Base address UART1 */ MCF_MBAR 41 arch/m68k/include/asm/m54xxsim.h #define MCFUART_BASE2 (MCF_MBAR + 0x8800) /* Base address UART2 */ MCF_MBAR 42 arch/m68k/include/asm/m54xxsim.h #define MCFUART_BASE3 (MCF_MBAR + 0x8900) /* Base address UART3 */ MCF_MBAR 58 arch/m68k/include/asm/m54xxsim.h #define MCFSLT_TIMER0 (MCF_MBAR + 0x900) /* Base addr TIMER0 */ MCF_MBAR 59 arch/m68k/include/asm/m54xxsim.h #define MCFSLT_TIMER1 (MCF_MBAR + 0x910) /* Base addr TIMER1 */ MCF_MBAR 64 arch/m68k/include/asm/m54xxsim.h #define MCFGPIO_PODR (MCF_MBAR + 0xA00) MCF_MBAR 65 arch/m68k/include/asm/m54xxsim.h #define MCFGPIO_PDDR (MCF_MBAR + 0xA10) MCF_MBAR 66 arch/m68k/include/asm/m54xxsim.h #define MCFGPIO_PPDR (MCF_MBAR + 0xA20) MCF_MBAR 67 arch/m68k/include/asm/m54xxsim.h #define MCFGPIO_SETR (MCF_MBAR + 0xA20) MCF_MBAR 68 arch/m68k/include/asm/m54xxsim.h #define MCFGPIO_CLRR (MCF_MBAR + 0xA30) MCF_MBAR 77 arch/m68k/include/asm/m54xxsim.h #define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */ MCF_MBAR 78 arch/m68k/include/asm/m54xxsim.h #define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */ MCF_MBAR 79 arch/m68k/include/asm/m54xxsim.h #define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */ MCF_MBAR 80 arch/m68k/include/asm/m54xxsim.h #define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */ MCF_MBAR 81 arch/m68k/include/asm/m54xxsim.h #define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */ MCF_MBAR 82 arch/m68k/include/asm/m54xxsim.h #define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */ MCF_MBAR 87 arch/m68k/include/asm/m54xxsim.h #define MCFGPIO_PAR_FBCTL (MCF_MBAR + 0xA40) MCF_MBAR 88 arch/m68k/include/asm/m54xxsim.h #define MCFGPIO_PAR_FBCS (MCF_MBAR + 0xA42) MCF_MBAR 89 arch/m68k/include/asm/m54xxsim.h #define MCFGPIO_PAR_DMA (MCF_MBAR + 0xA43) MCF_MBAR 90 arch/m68k/include/asm/m54xxsim.h #define MCFGPIO_PAR_FECI2CIRQ (MCF_MBAR + 0xA44) MCF_MBAR 91 arch/m68k/include/asm/m54xxsim.h #define MCFGPIO_PAR_PCIBG (MCF_MBAR + 0xA48) /* PCI bus grant */ MCF_MBAR 92 arch/m68k/include/asm/m54xxsim.h #define MCFGPIO_PAR_PCIBR (MCF_MBAR + 0xA4A) /* PCI */ MCF_MBAR 93 arch/m68k/include/asm/m54xxsim.h #define MCFGPIO_PAR_PSC0 (MCF_MBAR + 0xA4F) MCF_MBAR 94 arch/m68k/include/asm/m54xxsim.h #define MCFGPIO_PAR_PSC1 (MCF_MBAR + 0xA4E) MCF_MBAR 95 arch/m68k/include/asm/m54xxsim.h #define MCFGPIO_PAR_PSC2 (MCF_MBAR + 0xA4D) MCF_MBAR 96 arch/m68k/include/asm/m54xxsim.h #define MCFGPIO_PAR_PSC3 (MCF_MBAR + 0xA4C) MCF_MBAR 97 arch/m68k/include/asm/m54xxsim.h #define MCFGPIO_PAR_DSPI (MCF_MBAR + 0xA50) MCF_MBAR 98 arch/m68k/include/asm/m54xxsim.h #define MCFGPIO_PAR_TIMER (MCF_MBAR + 0xA52) MCF_MBAR 112 arch/m68k/include/asm/m54xxsim.h #define MCF_PAR_FECI2CIRQ (MCF_MBAR + 0x00000a44) /* FEC/I2C/IRQ */ MCF_MBAR 119 arch/m68k/include/asm/m54xxsim.h #define MCFI2C_BASE0 (MCF_MBAR + 0x8f00)