MCFSIM_ICR1        46 arch/m68k/coldfire/intc-5272.c 	/*MCF_IRQ_EINT1*/	{ .icr = MCFSIM_ICR1, .index = 28, .ack = 1, },
MCFSIM_ICR1        47 arch/m68k/coldfire/intc-5272.c 	/*MCF_IRQ_EINT2*/	{ .icr = MCFSIM_ICR1, .index = 24, .ack = 1, },
MCFSIM_ICR1        48 arch/m68k/coldfire/intc-5272.c 	/*MCF_IRQ_EINT3*/	{ .icr = MCFSIM_ICR1, .index = 20, .ack = 1, },
MCFSIM_ICR1        49 arch/m68k/coldfire/intc-5272.c 	/*MCF_IRQ_EINT4*/	{ .icr = MCFSIM_ICR1, .index = 16, .ack = 1, },
MCFSIM_ICR1        50 arch/m68k/coldfire/intc-5272.c 	/*MCF_IRQ_TIMER1*/	{ .icr = MCFSIM_ICR1, .index = 12, .ack = 0, },
MCFSIM_ICR1        51 arch/m68k/coldfire/intc-5272.c 	/*MCF_IRQ_TIMER2*/	{ .icr = MCFSIM_ICR1, .index = 8,  .ack = 0, },
MCFSIM_ICR1        52 arch/m68k/coldfire/intc-5272.c 	/*MCF_IRQ_TIMER3*/	{ .icr = MCFSIM_ICR1, .index = 4,  .ack = 0, },
MCFSIM_ICR1        53 arch/m68k/coldfire/intc-5272.c 	/*MCF_IRQ_TIMER4*/	{ .icr = MCFSIM_ICR1, .index = 0,  .ack = 0, },
MCFSIM_ICR1       166 arch/m68k/coldfire/intc-5272.c 	writel(0x88888888, MCFSIM_ICR1);
MCFSIM_ICR1       145 arch/m68k/include/asm/m525xsim.h #define MCFSIM_TIMER1ICR	MCFSIM_ICR1	/* Timer 1 ICR */
MCFSIM_ICR1       150 arch/m68k/include/asm/m5307sim.h #define	MCFSIM_TIMER1ICR	MCFSIM_ICR1	/* Timer 1 ICR */
MCFSIM_ICR1        68 arch/m68k/include/asm/m53xxsim.h #define	MCFSIM_TIMER1ICR	MCFSIM_ICR1	/* Timer 1 ICR */
MCFSIM_ICR1       114 arch/m68k/include/asm/m5407sim.h #define	MCFSIM_TIMER1ICR	MCFSIM_ICR1	/* Timer 1 ICR */