MBOX_INC_SEL_EXTAR_REG  529 arch/x86/events/intel/uncore_nhmex.c 	MBOX_INC_SEL_EXTAR_REG(0x0, DSP),
MBOX_INC_SEL_EXTAR_REG  530 arch/x86/events/intel/uncore_nhmex.c 	MBOX_INC_SEL_EXTAR_REG(0x4, MSC_THR),
MBOX_INC_SEL_EXTAR_REG  531 arch/x86/events/intel/uncore_nhmex.c 	MBOX_INC_SEL_EXTAR_REG(0x5, MSC_THR),
MBOX_INC_SEL_EXTAR_REG  532 arch/x86/events/intel/uncore_nhmex.c 	MBOX_INC_SEL_EXTAR_REG(0x9, ISS),
MBOX_INC_SEL_EXTAR_REG  534 arch/x86/events/intel/uncore_nhmex.c 	MBOX_INC_SEL_EXTAR_REG(0xa, ISS),
MBOX_INC_SEL_EXTAR_REG  535 arch/x86/events/intel/uncore_nhmex.c 	MBOX_INC_SEL_EXTAR_REG(0xa, PLD),
MBOX_INC_SEL_EXTAR_REG  536 arch/x86/events/intel/uncore_nhmex.c 	MBOX_INC_SEL_EXTAR_REG(0xb, PLD),
MBOX_INC_SEL_EXTAR_REG  538 arch/x86/events/intel/uncore_nhmex.c 	MBOX_INC_SEL_EXTAR_REG(0xd, ZDP_CTL_FVC),
MBOX_INC_SEL_EXTAR_REG  539 arch/x86/events/intel/uncore_nhmex.c 	MBOX_INC_SEL_EXTAR_REG(0xe, ZDP_CTL_FVC),
MBOX_INC_SEL_EXTAR_REG  540 arch/x86/events/intel/uncore_nhmex.c 	MBOX_INC_SEL_EXTAR_REG(0xf, ZDP_CTL_FVC),
MBOX_INC_SEL_EXTAR_REG  541 arch/x86/events/intel/uncore_nhmex.c 	MBOX_INC_SEL_EXTAR_REG(0x10, ZDP_CTL_FVC),
MBOX_INC_SEL_EXTAR_REG  542 arch/x86/events/intel/uncore_nhmex.c 	MBOX_INC_SEL_EXTAR_REG(0x16, PGT),