MAX_REGULAR_DPM_NUMBER  184 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h 	struct smu10_mclk_latency_entries  entries[MAX_REGULAR_DPM_NUMBER];
MAX_REGULAR_DPM_NUMBER  556 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					MAX_REGULAR_DPM_NUMBER);
MAX_REGULAR_DPM_NUMBER  636 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					MAX_REGULAR_DPM_NUMBER);
MAX_REGULAR_DPM_NUMBER  640 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER);
MAX_REGULAR_DPM_NUMBER  646 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					MAX_REGULAR_DPM_NUMBER);
MAX_REGULAR_DPM_NUMBER  650 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER);
MAX_REGULAR_DPM_NUMBER  656 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					MAX_REGULAR_DPM_NUMBER);
MAX_REGULAR_DPM_NUMBER  100 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h 	struct smu7_dpm_level	dpm_levels[MAX_REGULAR_DPM_NUMBER];
MAX_REGULAR_DPM_NUMBER  179 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h 	phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER];
MAX_REGULAR_DPM_NUMBER 1737 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	while (i < MAX_REGULAR_DPM_NUMBER) {
MAX_REGULAR_DPM_NUMBER 3457 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (table->count <= MAX_REGULAR_DPM_NUMBER) {
MAX_REGULAR_DPM_NUMBER 3464 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		return MAX_REGULAR_DPM_NUMBER - 1;
MAX_REGULAR_DPM_NUMBER  136 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h 	struct vega10_dpm_level	dpm_levels[MAX_REGULAR_DPM_NUMBER];
MAX_REGULAR_DPM_NUMBER  221 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h 	struct vega10_mclk_latency_entries  entries[MAX_REGULAR_DPM_NUMBER];
MAX_REGULAR_DPM_NUMBER  286 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h 	struct phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER];
MAX_REGULAR_DPM_NUMBER  291 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h 	struct phm_ppt_v1_voltage_lookup_record entries[MAX_REGULAR_DPM_NUMBER];
MAX_REGULAR_DPM_NUMBER 1021 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
MAX_REGULAR_DPM_NUMBER 1023 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			return MAX_REGULAR_DPM_NUMBER - 1);
MAX_REGULAR_DPM_NUMBER  110 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h 	struct vega12_dpm_level	dpm_levels[MAX_REGULAR_DPM_NUMBER];
MAX_REGULAR_DPM_NUMBER  115 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h 	uint32_t	entries[MAX_REGULAR_DPM_NUMBER];
MAX_REGULAR_DPM_NUMBER  212 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h 	struct vega12_mclk_latency_entries  entries[MAX_REGULAR_DPM_NUMBER];
MAX_REGULAR_DPM_NUMBER  285 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h 		entries[MAX_REGULAR_DPM_NUMBER];
MAX_REGULAR_DPM_NUMBER 1777 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
MAX_REGULAR_DPM_NUMBER 1779 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			return MAX_REGULAR_DPM_NUMBER - 1);
MAX_REGULAR_DPM_NUMBER  162 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h 	struct vega20_dpm_level	dpm_levels[MAX_REGULAR_DPM_NUMBER];
MAX_REGULAR_DPM_NUMBER  167 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h 	uint32_t	entries[MAX_REGULAR_DPM_NUMBER];
MAX_REGULAR_DPM_NUMBER  272 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h 	struct vega20_mclk_latency_entries  entries[MAX_REGULAR_DPM_NUMBER];
MAX_REGULAR_DPM_NUMBER  347 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h 		entries[MAX_REGULAR_DPM_NUMBER];
MAX_REGULAR_DPM_NUMBER 2323 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	if (table->count > MAX_REGULAR_DPM_NUMBER) {
MAX_REGULAR_DPM_NUMBER 2325 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		return MAX_REGULAR_DPM_NUMBER - 1;
MAX_REGULAR_DPM_NUMBER   99 drivers/gpu/drm/amd/powerplay/vega20_ppt.h         struct vega20_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
MAX_REGULAR_DPM_NUMBER 3381 drivers/gpu/drm/radeon/ci_dpm.c 	for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
MAX_REGULAR_DPM_NUMBER   65 drivers/gpu/drm/radeon/ci_dpm.h 	struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];