MAX_POST_DIVR_FREQ   82 drivers/clk/analogbits/wrpll-cln28hpc.c 	    post_divr_freq > MAX_POST_DIVR_FREQ) {
MAX_POST_DIVR_FREQ  195 drivers/clk/analogbits/wrpll-cln28hpc.c 	c->init_r = DIV_ROUND_UP_ULL(parent_rate, MAX_POST_DIVR_FREQ);