MAX_PIPES        2984 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	const struct pipe_ctx *active_pipes[MAX_PIPES];
MAX_PIPES         170 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES         134 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c 		for (k = 0; k < MAX_PIPES; k++)
MAX_PIPES         288 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES         316 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES         350 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES         356 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (i == MAX_PIPES)
MAX_PIPES         399 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES         405 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (i == MAX_PIPES)
MAX_PIPES         424 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES         461 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES         478 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES         502 drivers/gpu/drm/amd/display/dc/core/dc.c 	struct pipe_ctx *pipes_affected[MAX_PIPES];
MAX_PIPES         508 drivers/gpu/drm/amd/display/dc/core/dc.c 		for (j = 0; j < MAX_PIPES; j++) {
MAX_PIPES         847 drivers/gpu/drm/amd/display/dc/core/dc.c 	struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
MAX_PIPES         873 drivers/gpu/drm/amd/display/dc/core/dc.c 	struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
MAX_PIPES         884 drivers/gpu/drm/amd/display/dc/core/dc.c 		struct pipe_ctx *pipe_set[MAX_PIPES];
MAX_PIPES        1036 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES        1124 drivers/gpu/drm/amd/display/dc/core/dc.c 		for (k = 0; k < MAX_PIPES; k++) {
MAX_PIPES        1190 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES        1260 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES        1361 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (j = 0; j < MAX_PIPES; j++) {
MAX_PIPES         314 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 	int h_pos[MAX_PIPES] = {0}, v_pos[MAX_PIPES] = {0};
MAX_PIPES        2340 drivers/gpu/drm/amd/display/dc/core/dc_link.c 		for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES        3018 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES        3029 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	if (i == MAX_PIPES)
MAX_PIPES        3203 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES          84 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES         276 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES         464 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES        1058 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES        1134 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES        2453 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES         297 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES         344 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES         492 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES         520 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES         551 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES         580 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES         586 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	if (i == MAX_PIPES)
MAX_PIPES         609 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES         615 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	if (i == MAX_PIPES)
MAX_PIPES         474 drivers/gpu/drm/amd/display/dc/dc.h 	struct dc_link *links[MAX_PIPES * 2];
MAX_PIPES         189 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES         506 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 		for (k = 0; k < MAX_PIPES; k++)
MAX_PIPES         158 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	uint32_t PHASE[MAX_PIPES];
MAX_PIPES         159 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	uint32_t MODULO[MAX_PIPES];
MAX_PIPES         160 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h 	uint32_t PIXEL_RATE_CNTL[MAX_PIPES];
MAX_PIPES         964 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES        1653 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
MAX_PIPES        1694 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES        1886 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES        2897 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
MAX_PIPES         533 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
MAX_PIPES         830 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
MAX_PIPES        1371 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	ASSERT(stream_status->primary_otg_inst < MAX_PIPES);
MAX_PIPES        2051 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		for (j = 0; j < MAX_PIPES; j++)
MAX_PIPES        1611 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < MAX_PIPES; i++) {
MAX_PIPES        2482 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < MAX_PIPES; i++)
MAX_PIPES        2741 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	bool visited[MAX_PIPES] = { 0 };
MAX_PIPES        2846 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	int pipe_split_from[MAX_PIPES];
MAX_PIPES        1070 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	int pipe_split_from[MAX_PIPES];
MAX_PIPES         165 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct mem_input *mis[MAX_PIPES];
MAX_PIPES         166 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct hubp *hubps[MAX_PIPES];
MAX_PIPES         167 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct input_pixel_processor *ipps[MAX_PIPES];
MAX_PIPES         168 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct transform *transforms[MAX_PIPES];
MAX_PIPES         169 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct dpp *dpps[MAX_PIPES];
MAX_PIPES         170 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct output_pixel_processor *opps[MAX_PIPES];
MAX_PIPES         171 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct timing_generator *timing_generators[MAX_PIPES];
MAX_PIPES         172 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct stream_encoder *stream_enc[MAX_PIPES * 2];
MAX_PIPES         176 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct dce_aux *engines[MAX_PIPES];
MAX_PIPES         177 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct dce_i2c_hw *hw_i2cs[MAX_PIPES];
MAX_PIPES         178 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct dce_i2c_sw *sw_i2cs[MAX_PIPES];
MAX_PIPES         192 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct display_stream_compressor *dscs[MAX_PIPES];
MAX_PIPES         320 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct pipe_ctx pipe_ctx[MAX_PIPES];
MAX_PIPES         321 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	bool is_stream_enc_acquired[MAX_PIPES * 2];
MAX_PIPES         322 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	bool is_audio_acquired[MAX_PIPES];
MAX_PIPES         326 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	bool is_dsc_acquired[MAX_PIPES];
MAX_PIPES         336 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct dce_watermarks urgent_wm_ns[MAX_PIPES];
MAX_PIPES         337 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES];
MAX_PIPES         338 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES];
MAX_PIPES         339 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES];
MAX_PIPES         382 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct dc_stream_state *streams[MAX_PIPES];
MAX_PIPES         383 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct dc_stream_status stream_status[MAX_PIPES];
MAX_PIPES         200 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h 	int dpp[MAX_PIPES];
MAX_PIPES         201 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h 	int mpcc[MAX_PIPES];
MAX_PIPES         209 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h 	bool mpcc_disconnect_pending[MAX_PIPES];