MAX_OPP           361 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	for (opp_id = 0; opp_id < MAX_OPP; opp_id++) {
MAX_OPP           380 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 	if (opp_id < MAX_OPP && REG(MUX[opp_id]))
MAX_OPP            58 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 	uint32_t MUX[MAX_OPP];
MAX_OPP           121 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	uint32_t CSC_MODE[MAX_OPP]; \
MAX_OPP           122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	uint32_t CSC_C11_C12_A[MAX_OPP]; \
MAX_OPP           123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	uint32_t CSC_C33_C34_A[MAX_OPP]; \
MAX_OPP           124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	uint32_t CSC_C11_C12_B[MAX_OPP]; \
MAX_OPP           125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	uint32_t CSC_C33_C34_B[MAX_OPP]; \
MAX_OPP           126 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	uint32_t DENORM_CONTROL[MAX_OPP]; \
MAX_OPP           127 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	uint32_t DENORM_CLAMP_G_Y[MAX_OPP]; \
MAX_OPP           128 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h 	uint32_t DENORM_CLAMP_B_CB[MAX_OPP];