MAX_MPCC 488 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c for (i = 0; i < MAX_MPCC; i++) MAX_MPCC 49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h uint32_t MPCC_TOP_SEL[MAX_MPCC]; \ MAX_MPCC 50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h uint32_t MPCC_BOT_SEL[MAX_MPCC]; \ MAX_MPCC 51 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h uint32_t MPCC_CONTROL[MAX_MPCC]; \ MAX_MPCC 52 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h uint32_t MPCC_STATUS[MAX_MPCC]; \ MAX_MPCC 53 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h uint32_t MPCC_OPP_ID[MAX_MPCC]; \ MAX_MPCC 54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h uint32_t MPCC_BG_G_Y[MAX_MPCC]; \ MAX_MPCC 55 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h uint32_t MPCC_BG_R_CR[MAX_MPCC]; \ MAX_MPCC 56 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h uint32_t MPCC_BG_B_CB[MAX_MPCC]; \ MAX_MPCC 57 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h uint32_t MPCC_SM_CONTROL[MAX_MPCC]; \ MAX_MPCC 535 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c for (i = 0; i < MAX_MPCC; i++) MAX_MPCC 85 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_TOP_GAIN[MAX_MPCC]; \ MAX_MPCC 86 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_BOT_GAIN_INSIDE[MAX_MPCC]; \ MAX_MPCC 87 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_BOT_GAIN_OUTSIDE[MAX_MPCC]; \ MAX_MPCC 88 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_START_CNTL_B[MAX_MPCC]; \ MAX_MPCC 89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_START_CNTL_G[MAX_MPCC]; \ MAX_MPCC 90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_START_CNTL_R[MAX_MPCC]; \ MAX_MPCC 91 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_B[MAX_MPCC]; \ MAX_MPCC 92 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_G[MAX_MPCC]; \ MAX_MPCC 93 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_R[MAX_MPCC]; \ MAX_MPCC 94 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_END_CNTL1_B[MAX_MPCC]; \ MAX_MPCC 95 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_END_CNTL2_B[MAX_MPCC]; \ MAX_MPCC 96 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_END_CNTL1_G[MAX_MPCC]; \ MAX_MPCC 97 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_END_CNTL2_G[MAX_MPCC]; \ MAX_MPCC 98 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_END_CNTL1_R[MAX_MPCC]; \ MAX_MPCC 99 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_END_CNTL2_R[MAX_MPCC]; \ MAX_MPCC 100 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_REGION_0_1[MAX_MPCC]; \ MAX_MPCC 101 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMA_REGION_32_33[MAX_MPCC]; \ MAX_MPCC 102 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_START_CNTL_B[MAX_MPCC]; \ MAX_MPCC 103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_START_CNTL_G[MAX_MPCC]; \ MAX_MPCC 104 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_START_CNTL_R[MAX_MPCC]; \ MAX_MPCC 105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_B[MAX_MPCC]; \ MAX_MPCC 106 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_G[MAX_MPCC]; \ MAX_MPCC 107 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_R[MAX_MPCC]; \ MAX_MPCC 108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_END_CNTL1_B[MAX_MPCC]; \ MAX_MPCC 109 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_END_CNTL2_B[MAX_MPCC]; \ MAX_MPCC 110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_END_CNTL1_G[MAX_MPCC]; \ MAX_MPCC 111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_END_CNTL2_G[MAX_MPCC]; \ MAX_MPCC 112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_END_CNTL1_R[MAX_MPCC]; \ MAX_MPCC 113 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_END_CNTL2_R[MAX_MPCC]; \ MAX_MPCC 114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_REGION_0_1[MAX_MPCC]; \ MAX_MPCC 115 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_RAMB_REGION_32_33[MAX_MPCC];\ MAX_MPCC 116 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_MEM_PWR_CTRL[MAX_MPCC];\ MAX_MPCC 117 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_LUT_INDEX[MAX_MPCC];\ MAX_MPCC 118 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_LUT_RAM_CONTROL[MAX_MPCC];\ MAX_MPCC 119 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_LUT_DATA[MAX_MPCC];\ MAX_MPCC 120 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h uint32_t MPCC_OGAM_MODE[MAX_MPCC];\ MAX_MPCC 128 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h struct mpcc mpcc_array[MAX_MPCC];