MAX_INSTANCE 34 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c for (i = 0 ; i < MAX_INSTANCE ; ++i) { MAX_INSTANCE 34 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c for (i = 0 ; i < MAX_INSTANCE ; ++i) { MAX_INSTANCE 34 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c for (i = 0 ; i < MAX_INSTANCE ; ++i) { MAX_INSTANCE 34 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c for (i = 0 ; i < MAX_INSTANCE ; ++i) { MAX_INSTANCE 34 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c for (i = 0 ; i < MAX_INSTANCE ; ++i) { MAX_INSTANCE 34 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c for (i = 0 ; i < MAX_INSTANCE ; ++i) { MAX_INSTANCE 38 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; MAX_INSTANCE 35 drivers/gpu/drm/amd/include/arct_ip_offset.h struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; MAX_INSTANCE 33 drivers/gpu/drm/amd/include/navi10_ip_offset.h struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; MAX_INSTANCE 35 drivers/gpu/drm/amd/include/navi12_ip_offset.h struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; MAX_INSTANCE 35 drivers/gpu/drm/amd/include/navi14_ip_offset.h struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; MAX_INSTANCE 35 drivers/gpu/drm/amd/include/renoir_ip_offset.h struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; MAX_INSTANCE 34 drivers/gpu/drm/amd/include/vega10_ip_offset.h struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; MAX_INSTANCE 35 drivers/gpu/drm/amd/include/vega20_ip_offset.h struct IP_BASE_INSTANCE instance[MAX_INSTANCE];