MAX_DFLL_VOLTAGES  302 drivers/clk/tegra/clk-dfll.c 	unsigned			lut[MAX_DFLL_VOLTAGES];
MAX_DFLL_VOLTAGES  303 drivers/clk/tegra/clk-dfll.c 	unsigned long			lut_uv[MAX_DFLL_VOLTAGES];
MAX_DFLL_VOLTAGES  680 drivers/clk/tegra/clk-dfll.c 	for (i = 0; i < MAX_DFLL_VOLTAGES; i++) {
MAX_DFLL_VOLTAGES 1352 drivers/clk/tegra/clk-dfll.c 		for (offs = 0; offs <  4 * MAX_DFLL_VOLTAGES; offs += 4)
MAX_DFLL_VOLTAGES 1589 drivers/clk/tegra/clk-dfll.c 	u8 lut_bottom = MAX_DFLL_VOLTAGES;
MAX_DFLL_VOLTAGES 1592 drivers/clk/tegra/clk-dfll.c 	for (i = 0; i < MAX_DFLL_VOLTAGES; i++) {
MAX_DFLL_VOLTAGES 1601 drivers/clk/tegra/clk-dfll.c 		if ((lut_bottom == MAX_DFLL_VOLTAGES) && (reg_volt >= v_min))
MAX_DFLL_VOLTAGES 1607 drivers/clk/tegra/clk-dfll.c 	if ((lut_bottom == MAX_DFLL_VOLTAGES) ||
MAX_DFLL_VOLTAGES 1667 drivers/clk/tegra/clk-dfll.c 			v += max(1UL, (v_max - v) / (MAX_DFLL_VOLTAGES - j));
MAX_DFLL_VOLTAGES 1678 drivers/clk/tegra/clk-dfll.c 		v = (j == MAX_DFLL_VOLTAGES - 1) ? v_max : v_opp;
MAX_DFLL_VOLTAGES 1796 drivers/clk/tegra/clk-dfll.c 	for (i = 0; i < MAX_DFLL_VOLTAGES; i++)
MAX_DFLL_VOLTAGES 1812 drivers/clk/tegra/clk-dfll.c 	td->pwm_rate = (NSEC_PER_SEC / pwm_period) * (MAX_DFLL_VOLTAGES - 1);