MAX_CHANNELS_PER_ENC  181 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
MAX_CHANNELS_PER_ENC  957 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL };
MAX_CHANNELS_PER_ENC  958 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	struct dpu_hw_mixer *hw_lm[MAX_CHANNELS_PER_ENC] = { NULL };
MAX_CHANNELS_PER_ENC 1004 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
MAX_CHANNELS_PER_ENC 1012 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
MAX_CHANNELS_PER_ENC 1020 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
MAX_CHANNELS_PER_ENC 1059 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 			for (j = 0; j < MAX_CHANNELS_PER_ENC; j++) {