MASK 37 arch/arm/mach-rpc/irq.c val = readb(base + MASK); MASK 38 arch/arm/mach-rpc/irq.c writeb(val & ~mask, base + MASK); MASK 47 arch/arm/mach-rpc/irq.c val = readb(base + MASK); MASK 48 arch/arm/mach-rpc/irq.c writeb(val & ~mask, base + MASK); MASK 56 arch/arm/mach-rpc/irq.c val = readb(base + MASK); MASK 57 arch/arm/mach-rpc/irq.c writeb(val | mask, base + MASK); MASK 53 arch/ia64/kernel/ptrace.c #define PFM_MASK MASK(38) MASK 83 arch/ia64/kernel/ptrace.c unsigned long mask = MASK(nbits) << first; \ MASK 122 arch/ia64/kernel/ptrace.c unsigned long mask = MASK(nbits) << first; \ MASK 270 arch/ia64/kernel/ptrace.c mask = MASK(nbits); MASK 285 arch/ia64/kernel/ptrace.c umask = MASK(ia64_rse_slot_num(ubspstore)) & mask; MASK 343 arch/ia64/kernel/ptrace.c mask = MASK(nbits); MASK 359 arch/ia64/kernel/ptrace.c umask = MASK(ia64_rse_slot_num(ubspstore)) & mask; MASK 94 arch/x86/kernel/cpu/mce/severity.c NOSER, MASK(MCI_STATUS_UC|MCI_STATUS_DEFERRED|MCI_STATUS_POISON, MCI_STATUS_DEFERRED) MASK 110 arch/x86/kernel/cpu/mce/severity.c SER, MASK(MCI_UC_AR|MCACOD_SCRUBMSK, MCI_STATUS_UC|MCACOD_SCRUB) MASK 114 arch/x86/kernel/cpu/mce/severity.c SER, MASK(MCI_UC_AR|MCACOD, MCI_STATUS_UC|MCACOD_L3WB) MASK 120 arch/x86/kernel/cpu/mce/severity.c SER, MASK(MCI_UC_SAR, MCI_STATUS_UC) MASK 125 arch/x86/kernel/cpu/mce/severity.c MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_UC|MCI_STATUS_AR) MASK 141 arch/x86/kernel/cpu/mce/severity.c SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR, MCI_UC_SAR|MCI_ADDR), MASK 146 arch/x86/kernel/cpu/mce/severity.c SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA), MASK 151 arch/x86/kernel/cpu/mce/severity.c SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA), MASK 156 arch/x86/kernel/cpu/mce/severity.c SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR), MASK 161 arch/x86/kernel/cpu/mce/severity.c SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA), MASK 166 arch/x86/kernel/cpu/mce/severity.c SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR), MASK 172 arch/x86/kernel/cpu/mce/severity.c SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_SAR) MASK 177 arch/x86/kernel/cpu/mce/severity.c SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_S) MASK 181 arch/x86/kernel/cpu/mce/severity.c SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_OVER|MCI_UC_S) MASK 127 drivers/char/xilinx_hwicap/xilinx_hwicap.c .MASK = 6, MASK 152 drivers/char/xilinx_hwicap/xilinx_hwicap.c .MASK = 6, MASK 177 drivers/char/xilinx_hwicap/xilinx_hwicap.c .MASK = 6, MASK 202 drivers/char/xilinx_hwicap/xilinx_hwicap.c .MASK = 6, MASK 131 drivers/char/xilinx_hwicap/xilinx_hwicap.h u32 MASK; MASK 135 drivers/clk/tegra/clk-tegra-periph.c 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ MASK 142 drivers/clk/tegra/clk-tegra-periph.c 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ MASK 149 drivers/clk/tegra/clk-tegra-periph.c 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ MASK 155 drivers/clk/tegra/clk-tegra-periph.c 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ MASK 161 drivers/clk/tegra/clk-tegra-periph.c 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ MASK 168 drivers/clk/tegra/clk-tegra-periph.c 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ MASK 175 drivers/clk/tegra/clk-tegra-periph.c 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ MASK 182 drivers/clk/tegra/clk-tegra-periph.c 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ MASK 189 drivers/clk/tegra/clk-tegra-periph.c 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \ MASK 196 drivers/clk/tegra/clk-tegra-periph.c 29, MASK(3), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \ MASK 203 drivers/clk/tegra/clk-tegra-periph.c 30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\ MASK 210 drivers/clk/tegra/clk-tegra-periph.c 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ MASK 758 drivers/clk/tegra/clk-tegra-periph.c NODIV("xusb_hs_src", mux_ss_div2_60M, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src, NULL), MASK 759 drivers/clk/tegra/clk-tegra-periph.c NODIV("xusb_hs_src", mux_ss_div2_60M_ss, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(2), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src_4, NULL), MASK 760 drivers/clk/tegra/clk-tegra-periph.c NODIV("xusb_ssp_src", mux_ss_clkm, CLK_SOURCE_XUSB_SS_SRC, 24, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ssp_src, NULL), MASK 118 drivers/clk/tegra/clk-tegra114.c 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ MASK 127 drivers/dma/dw/core.c channel_set_bit(dw, MASK.XFER, dwc->mask); MASK 128 drivers/dma/dw/core.c channel_set_bit(dw, MASK.ERROR, dwc->mask); MASK 495 drivers/dma/dw/core.c channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); MASK 496 drivers/dma/dw/core.c channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); MASK 519 drivers/dma/dw/core.c channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); MASK 520 drivers/dma/dw/core.c channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); MASK 521 drivers/dma/dw/core.c channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); MASK 530 drivers/dma/dw/core.c channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); MASK 531 drivers/dma/dw/core.c channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); MASK 532 drivers/dma/dw/core.c channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); MASK 533 drivers/dma/dw/core.c channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); MASK 534 drivers/dma/dw/core.c channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); MASK 961 drivers/dma/dw/core.c channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); MASK 962 drivers/dma/dw/core.c channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); MASK 963 drivers/dma/dw/core.c channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); MASK 964 drivers/dma/dw/core.c channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); MASK 965 drivers/dma/dw/core.c channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); MASK 1038 drivers/dma/dw/core.c channel_clear_bit(dw, MASK.XFER, dwc->mask); MASK 1039 drivers/dma/dw/core.c channel_clear_bit(dw, MASK.BLOCK, dwc->mask); MASK 1040 drivers/dma/dw/core.c channel_clear_bit(dw, MASK.ERROR, dwc->mask); MASK 70 drivers/dma/dw/regs.h struct dw_dma_irq_regs MASK; /* rw (set = irq enabled) */ MASK 41 drivers/dma/idma64.c channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask); MASK 42 drivers/dma/idma64.c channel_clear_bit(idma64, MASK(BLOCK), idma64->all_chan_mask); MASK 43 drivers/dma/idma64.c channel_clear_bit(idma64, MASK(SRC_TRAN), idma64->all_chan_mask); MASK 44 drivers/dma/idma64.c channel_clear_bit(idma64, MASK(DST_TRAN), idma64->all_chan_mask); MASK 45 drivers/dma/idma64.c channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask); MASK 71 drivers/dma/idma64.c channel_set_bit(idma64, MASK(XFER), idma64c->mask); MASK 72 drivers/dma/idma64.c channel_set_bit(idma64, MASK(ERROR), idma64c->mask); MASK 41 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h DDC_GPIO_REG_LIST_ENTRY(MASK,cd,id),\ MASK 66 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h DDC_GPIO_VGA_REG_LIST_ENTRY(MASK,cd),\ MASK 83 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h DDC_GPIO_I2C_REG_LIST_ENTRY(MASK,cd),\ MASK 38 drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h GENERIC_GPIO_REG_LIST_ENTRY(MASK, cd, id),\ MASK 46 drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h HPD_GPIO_REG_LIST_ENTRY(MASK,cd,id),\ MASK 45 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c REG_GET(MASK_reg, MASK, &gpio->store.mask); MASK 54 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c REG_UPDATE(MASK_reg, MASK, gpio->store.mask); MASK 152 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c REG_UPDATE(MASK_reg, MASK, 1); MASK 158 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c REG_UPDATE(MASK_reg, MASK, 1); MASK 164 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c REG_UPDATE(MASK_reg, MASK, 1); MASK 168 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c REG_UPDATE(MASK_reg, MASK, 0); MASK 172 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c REG_UPDATE(MASK_reg, MASK, 0); MASK 350 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dw_update_bits(base + PHY_TMR_CFG, 24, MASK(8), phy->hs2lp_time); MASK 351 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dw_update_bits(base + PHY_TMR_CFG, 16, MASK(8), phy->lp2hs_time); MASK 352 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dw_update_bits(base + PHY_TMR_LPCLK_CFG, 16, MASK(10), MASK 354 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dw_update_bits(base + PHY_TMR_LPCLK_CFG, 0, MASK(10), MASK 356 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dw_update_bits(base + CLK_DATA_TMR_CFG, 8, MASK(8), MASK 358 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dw_update_bits(base + CLK_DATA_TMR_CFG, 0, MASK(8), MASK 17 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h #define FRM_END_START_MASK MASK(2) MASK 50 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h #define CH_OVLY_SEL_MASK MASK(2) MASK 99 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h #define QOSGENERATOR_MODE_MASK MASK(2) MASK 102 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c MASK(1), !!val); MASK 128 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(MASK(32), base + ADE_SOFT_RST_SEL(0)); MASK 129 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(MASK(32), base + ADE_SOFT_RST_SEL(1)); MASK 130 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(MASK(32), base + ADE_RELOAD_DIS(0)); MASK 131 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c writel(MASK(32), base + ADE_RELOAD_DIS(1)); MASK 285 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c MASK(1), 1); MASK 302 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c MASK(1), 0); MASK 318 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c MASK(1), 1); MASK 700 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c MASK(1), 0); MASK 114 drivers/gpu/drm/i915/i915_syncmap.c return (id >> p->height) & MASK; MASK 121 drivers/gpu/drm/i915/i915_syncmap.c return id & MASK; MASK 305 drivers/gpu/drm/i915/i915_syncmap.c idx = p->prefix >> (above - SHIFT) & MASK; MASK 414 drivers/gpu/drm/i915/selftests/i915_syncmap.c u64 context = i915_prandom_u64_state(&prng) & ~MASK; MASK 358 drivers/gpu/drm/nouveau/dispnv04/crtc.c regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) | MASK 388 drivers/gpu/drm/nouveau/dispnv04/crtc.c MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00; MASK 732 drivers/gpu/drm/nouveau/dispnv04/crtc.c tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG); MASK 46 drivers/gpu/drm/nouveau/dispnv04/cursor.c MASK(NV_CIO_CRE_HCUR_ASI) | MASK 52 drivers/gpu/drm/nouveau/dispnv04/cursor.c MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL); MASK 167 drivers/gpu/drm/nouveau/dispnv04/dac.c saved_pi & ~(0x80 | MASK(NV_CIO_CRE_PIXEL_FORMAT))); MASK 35 drivers/gpu/drm/nouveau/dispnv04/hw.h (((src) >> (srclowbit)) << (0 ? outfield)) & MASK(outfield)) MASK 379 drivers/gpu/drm/nouveau/dispnv04/hw.h *curctl1 |= MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE); MASK 381 drivers/gpu/drm/nouveau/dispnv04/hw.h *curctl1 &= ~MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE); MASK 71 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); MASK 72 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); MASK 73 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); MASK 82 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c val = (pll->m & MASK(GPCPLL_COEFF_M_WIDTH)) << GPCPLL_COEFF_M_SHIFT; MASK 83 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c val |= (pll->n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT; MASK 84 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c val |= (pll->pl & MASK(GPCPLL_COEFF_P_WIDTH)) << GPCPLL_COEFF_P_SHIFT; MASK 49 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h (MASK(GPCPLL_CFG3_VCO_CTRL_WIDTH) << GPCPLL_CFG3_VCO_CTRL_SHIFT) MASK 59 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h (MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT) MASK 87 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h #define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \ MASK 92 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h #define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \ MASK 94 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\ MASK 95 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT)) MASK 41 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c (MASK(GPCPLL_CFG2_SDM_DIN_WIDTH) << GPCPLL_CFG2_SDM_DIN_SHIFT) MASK 45 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c (MASK(GPCPLL_CFG2_SDM_DIN_NEW_WIDTH) << GPCPLL_CFG2_SDM_DIN_NEW_SHIFT) MASK 53 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c (MASK(GPCPLL_DVFS0_DFS_COEFF_WIDTH) << GPCPLL_DVFS0_DFS_COEFF_SHIFT) MASK 57 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c (MASK(GPCPLL_DVFS0_DFS_DET_MAX_WIDTH) << GPCPLL_DVFS0_DFS_DET_MAX_SHIFT) MASK 169 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c MASK(GPCPLL_CFG2_SDM_DIN_WIDTH); MASK 201 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c dvfs->dfs_coeff = min_t(u32, coeff, MASK(GPCPLL_DVFS0_DFS_COEFF_WIDTH)); MASK 254 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c rem = ((u32)n) & MASK(DFS_DET_RANGE); MASK 259 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c *sdm_din = (rem >> BITS_PER_BYTE) & MASK(GPCPLL_CFG2_SDM_DIN_WIDTH); MASK 536 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c nvkm_mask(device, GPC_BCAST_GPCPLL_DVFS2, MASK(DFS_DET_RANGE + 1), MASK 788 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c data &= MASK(GPCPLL_CFG3_PLL_DFS_TESTOUT_WIDTH); MASK 829 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c MASK(BYPASSCTRL_SYS_GPCPLL_WIDTH) << BYPASSCTRL_SYS_GPCPLL_SHIFT, MASK 954 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c MASK(FUSE_RESERVED_CALIB0_FUSE_REV_WIDTH); MASK 963 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c MASK(FUSE_RESERVED_CALIB0_SLOPE_INT_WIDTH)) * 1000 + MASK 965 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c MASK(FUSE_RESERVED_CALIB0_SLOPE_FRAC_WIDTH)); MASK 969 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c MASK(FUSE_RESERVED_CALIB0_INTERCEPT_INT_WIDTH)) * 1000 + MASK 971 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c MASK(FUSE_RESERVED_CALIB0_INTERCEPT_FRAC_WIDTH)) * 100; MASK 652 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c x_mask = MASK(x_bits); MASK 653 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c y_mask = MASK(y_bits); MASK 1150 drivers/infiniband/hw/hfi1/file_ops.c HFI1_CAP_UGET_MASK(uctxt->flags, MASK) | MASK 516 drivers/media/tuners/tda18250.c [MASK] = { 0x77, 0xff, 0xff, 0x87, 0xf0, 0x78, 0x07, 0xe0, MASK 587 drivers/media/tuners/tda18250.c delsys_params[MASK][i], delsys_params[j][i]); MASK 560 drivers/mfd/asic3.c asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff); MASK 561 drivers/mfd/asic3.c asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff); MASK 562 drivers/mfd/asic3.c asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff); MASK 563 drivers/mfd/asic3.c asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff); MASK 146 drivers/net/ethernet/atheros/alx/hw.h #define DESC_GET(_x, _name) ((_x) >> _name##SHIFT & _name##MASK) MASK 20 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) MASK 1110 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c (off & MASK(16)); MASK 18 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) MASK 1143 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c *addr = ahw->pci_base0 + CRB_INDIRECT_2M + (off & MASK(16)); MASK 369 drivers/platform/x86/compal-laptop.c #define SIMPLE_MASKED_STORE_SHOW(NAME, ADDR, MASK) \ MASK 373 drivers/platform/x86/compal-laptop.c return sprintf(buf, "%d\n", ((ec_read_u8(ADDR) & MASK) != 0)); \ MASK 382 drivers/platform/x86/compal-laptop.c ec_write(ADDR, state ? (old_val | MASK) : (old_val & ~MASK)); \ MASK 67 drivers/platform/x86/intel_telemetry_debugfs.c #define TELEM_CHECK_AND_PARSE_EVTS(EVTID, EVTNUM, BUF, EVTLOG, EVTDAT, MASK) { \ MASK 71 drivers/platform/x86/intel_telemetry_debugfs.c (MASK); \ MASK 528 drivers/scsi/aic7xxx/aicasm/aicasm_gram.y process_field(MASK, $2, $3.value); MASK 707 drivers/scsi/aic7xxx/aicasm/aicasm_gram.y case MASK: MASK 1436 drivers/scsi/aic7xxx/aicasm/aicasm_gram.y if (field_type != MASK && value == 0) { MASK 1510 drivers/scsi/aic7xxx/aicasm/aicasm_gram.y case MASK: MASK 1895 drivers/scsi/aic7xxx/aicasm/aicasm_gram.y if ((node->symbol->type == MASK MASK 101 drivers/scsi/aic7xxx/aicasm/aicasm_symbol.c case MASK: MASK 243 drivers/scsi/aic7xxx/aicasm/aicasm_symbol.c case MASK: MASK 501 drivers/scsi/aic7xxx/aicasm/aicasm_symbol.c case MASK: MASK 628 drivers/scsi/aic7xxx/aicasm/aicasm_symbol.c case MASK: MASK 2425 drivers/scsi/ncr53c8xx.c SCR_JUMP ^ IFTRUE (MASK (0, (HS_DONEMASK|HS_SKIPMASK))), MASK 2874 drivers/scsi/ncr53c8xx.c SCR_JUMPR ^ IFFALSE (MASK (0, HS_DONEMASK)), MASK 2952 drivers/scsi/ncr53c8xx.c SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)), MASK 3288 drivers/scsi/ncr53c8xx.c SCR_JUMPR ^ IFTRUE (MASK (0x80, 0x80)), MASK 7449 drivers/scsi/ncr53c8xx.c cpu_to_scr((SCR_JUMP ^ IFTRUE (MASK (i, 3)))); MASK 7539 drivers/scsi/ncr53c8xx.c cpu_to_scr((SCR_JUMP ^ IFFALSE (MASK (0x80+ln, 0xff)))); MASK 8434 drivers/scsi/ncr53c8xx.c cpu_to_scr((SCR_JUMP ^ IFTRUE (MASK (i, 3)))); MASK 25 drivers/scsi/qla2xxx/qla_nx.c #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) MASK 380 drivers/scsi/qla2xxx/qla_nx.c *off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; MASK 26 drivers/scsi/qla4xxx/ql4_nx.c #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) MASK 376 drivers/scsi/qla4xxx/ql4_nx.c *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; MASK 236 drivers/scsi/sym53c8xx_2/sym_fw1.h SCR_INT ^ IFTRUE (MASK (SEM, SEM)), MASK 363 drivers/scsi/sym53c8xx_2/sym_fw1.h SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)), MASK 453 drivers/scsi/sym53c8xx_2/sym_fw1.h SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)), MASK 478 drivers/scsi/sym53c8xx_2/sym_fw1.h SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)), MASK 538 drivers/scsi/sym53c8xx_2/sym_fw1.h SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)), MASK 704 drivers/scsi/sym53c8xx_2/sym_fw1.h SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))), MASK 949 drivers/scsi/sym53c8xx_2/sym_fw1.h SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)), MASK 955 drivers/scsi/sym53c8xx_2/sym_fw1.h SCR_INT ^ IFFALSE (MASK (0x80, 0x80)), MASK 1187 drivers/scsi/sym53c8xx_2/sym_fw1.h SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), MASK 1207 drivers/scsi/sym53c8xx_2/sym_fw1.h SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), MASK 1263 drivers/scsi/sym53c8xx_2/sym_fw1.h SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), MASK 1283 drivers/scsi/sym53c8xx_2/sym_fw1.h SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), MASK 1390 drivers/scsi/sym53c8xx_2/sym_fw1.h SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)), MASK 1392 drivers/scsi/sym53c8xx_2/sym_fw1.h SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)), MASK 1398 drivers/scsi/sym53c8xx_2/sym_fw1.h SCR_JUMP ^ IFFALSE (MASK (0x20, 0xf0)), MASK 1591 drivers/scsi/sym53c8xx_2/sym_fw1.h SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)), MASK 228 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_INT ^ IFTRUE (MASK (SEM, SEM)), MASK 316 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_INT ^ IFTRUE (MASK (HX_DMAP_DIRTY, HX_DMAP_DIRTY)), MASK 348 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)), MASK 438 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)), MASK 462 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)), MASK 521 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)), MASK 681 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))), MASK 898 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)), MASK 904 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_INT ^ IFFALSE (MASK (0x80, 0x80)), MASK 1073 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), MASK 1093 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), MASK 1138 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)), MASK 1158 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)), MASK 1269 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)), MASK 1271 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)), MASK 1277 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_JUMP ^ IFFALSE (MASK (0x20, 0xf0)), MASK 1464 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)), MASK 1612 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED))), MASK 1619 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_JUMPR ^ IFFALSE (MASK (HF_DP_SAVED, HF_DP_SAVED)), MASK 1630 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_JUMP ^ IFTRUE (MASK (0, (HF_IN_PM0 | HF_IN_PM1))), MASK 1632 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_JUMPR ^ IFFALSE (MASK (HF_IN_PM0, HF_IN_PM0)), MASK 1663 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_JUMP ^ IFTRUE (MASK (HF_ACT_PM, HF_ACT_PM)), MASK 1675 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_CALL ^ IFTRUE (MASK (WSR, WSR)), MASK 1705 drivers/scsi/sym53c8xx_2/sym_fw2.h SCR_CALL ^ IFTRUE (MASK (WSR, WSR)), MASK 653 drivers/scsi/vmw_pvscsi.c MASK(cmp_entries)); MASK 703 drivers/scsi/vmw_pvscsi.c e = adapter->req_ring + (s->reqProdIdx & MASK(req_entries)); MASK 1092 drivers/scsi/vmw_pvscsi.c MASK(msg_entries)); MASK 412 drivers/scsi/vmw_pvscsi.h #define PVSCSI_INTR_CMPL_MASK MASK(2) MASK 416 drivers/scsi/vmw_pvscsi.h #define PVSCSI_INTR_MSG_MASK (MASK(2) << 2) MASK 418 drivers/scsi/vmw_pvscsi.h #define PVSCSI_INTR_ALL_SUPPORTED MASK(4) MASK 636 drivers/tty/n_tty.c while (MASK(ldata->echo_commit) != MASK(tail)) { MASK 647 drivers/tty/n_tty.c if (MASK(ldata->echo_commit) == MASK(tail + 1)) MASK 660 drivers/tty/n_tty.c if (MASK(ldata->echo_commit) == MASK(tail + 2)) MASK 1013 drivers/tty/n_tty.c while (MASK(ldata->read_head) != MASK(ldata->canon_head)) { MASK 1021 drivers/tty/n_tty.c MASK(head) != MASK(ldata->canon_head)); MASK 1063 drivers/tty/n_tty.c while (MASK(tail) != MASK(ldata->canon_head)) { MASK 1338 drivers/tty/n_tty.c while (MASK(tail) != MASK(ldata->read_head)) { MASK 2439 drivers/tty/n_tty.c while (MASK(head) != MASK(tail)) { MASK 172 include/linux/irqchip/arm-gic-v3.h GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK) MASK 174 include/linux/irqchip/arm-gic-v3.h GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK) MASK 199 include/linux/irqchip/arm-gic-v3.h GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK) MASK 201 include/linux/irqchip/arm-gic-v3.h GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK) MASK 257 include/linux/irqchip/arm-gic-v3.h GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, MASK) MASK 259 include/linux/irqchip/arm-gic-v3.h GIC_BASER_CACHEABILITY(GICR_VPROPBASER, OUTER, MASK) MASK 283 include/linux/irqchip/arm-gic-v3.h GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, MASK) MASK 285 include/linux/irqchip/arm-gic-v3.h GIC_BASER_CACHEABILITY(GICR_VPENDBASER, OUTER, MASK) MASK 358 include/linux/irqchip/arm-gic-v3.h GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK) MASK 360 include/linux/irqchip/arm-gic-v3.h GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK) MASK 385 include/linux/irqchip/arm-gic-v3.h GIC_BASER_CACHEABILITY(GITS_BASER, INNER, MASK) MASK 388 include/linux/irqchip/arm-gic-v3.h GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, MASK) MASK 26 include/linux/soc/ti/knav_dma.h #define KNAV_DMA_DESC_PKT_LEN_MASK MASK(22) MASK 30 include/linux/soc/ti/knav_dma.h #define KNAV_DMA_DESC_TAG_MASK MASK(8) MASK 38 include/linux/soc/ti/knav_dma.h #define KNAV_DMA_DESC_PSLEN_MASK MASK(6) MASK 40 include/linux/soc/ti/knav_dma.h #define KNAV_DMA_DESC_ERR_FLAG_MASK MASK(4) MASK 42 include/linux/soc/ti/knav_dma.h #define KNAV_DMA_DESC_PSFLAG_MASK MASK(4) MASK 44 include/linux/soc/ti/knav_dma.h #define KNAV_DMA_DESC_RETQ_MASK MASK(14) MASK 45 include/linux/soc/ti/knav_dma.h #define KNAV_DMA_DESC_BUF_LEN_MASK MASK(22) MASK 46 include/linux/soc/ti/knav_dma.h #define KNAV_DMA_DESC_EFLAGS_MASK MASK(4) MASK 84 include/video/gbe.h ( ((u32)(v) & MASK(msb,lsb)) >> (lsb) ) MASK 86 include/video/gbe.h ( (v) = ((v)&~MASK(msb,lsb)) | (( (u32)(f)<<(lsb) ) & MASK(msb,lsb)) ) MASK 2080 kernel/debug/kdb/kdb_main.c if (KDB_DEBUG(MASK)) MASK 621 net/mac80211/debugfs_sta.c "TF-MAC-PAD-DUR-%dUS", MASK, "UNKNOWN"); MASK 242 net/openvswitch/datapath.h #define OVS_MASKED(OLD, KEY, MASK) ((KEY) | ((OLD) & ~(MASK))) MASK 243 net/openvswitch/datapath.h #define OVS_SET_MASKED(OLD, KEY, MASK) ((OLD) = OVS_MASKED(OLD, KEY, MASK)) MASK 798 sound/drivers/vx/vx_mixer.c .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), MASK 484 sound/i2c/cs8427.c .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), MASK 399 sound/i2c/other/ak4113.c .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK), MASK 363 sound/i2c/other/ak4114.c .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), MASK 378 sound/i2c/other/ak4114.c .name = SNDRV_CTL_NAME_IEC958("",CAPTURE,MASK), MASK 350 sound/i2c/other/ak4117.c .name = SNDRV_CTL_NAME_IEC958("",CAPTURE,MASK), MASK 578 sound/pci/ca0106/ca0106_mixer.c .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), MASK 2325 sound/pci/cs46xx/cs46xx_lib.c .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), MASK 675 sound/pci/ctxfi/ctmixer.c .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK), MASK 1157 sound/pci/emu10k1/emu10k1x.c .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), MASK 1170 sound/pci/emu10k1/emumixer.c .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), MASK 1468 sound/pci/ens1370.c .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), MASK 1834 sound/pci/ice1712/aureon.c .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK), MASK 819 sound/pci/oxygen/oxygen_mixer.c .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK), MASK 1010 sound/pci/pcxhr/pcxhr_mixer.c .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), MASK 1026 sound/pci/pcxhr/pcxhr_mixer.c .name = SNDRV_CTL_NAME_IEC958("",CAPTURE,MASK), MASK 2445 sound/pci/trident/trident_main.c .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), MASK 575 sound/soc/img/img-spdif-in.c .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK), MASK 190 sound/soc/img/img-spdif-out.c .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK), MASK 326 sound/soc/meson/axg-spdifin.c .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK), \ MASK 1681 sound/usb/mixer_quirks.c .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK), MASK 1490 sound/x86/intel_hdmi_audio.c .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK), MASK 58 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[64] = REG(MASK); MASK 13 tools/testing/selftests/bpf/progs/test_pkt_md_access.c #define TEST_FIELD(TYPE, FIELD, MASK) \ MASK 16 tools/testing/selftests/bpf/progs/test_pkt_md_access.c if (tmp != ((*(volatile __u32 *)&skb->FIELD) & MASK)) \ MASK 21 tools/testing/selftests/bpf/progs/test_pkt_md_access.c #define TEST_FIELD(TYPE, FIELD, MASK) \ MASK 25 tools/testing/selftests/bpf/progs/test_pkt_md_access.c if (tmp != ((*(volatile __u32 *)&skb->FIELD) & MASK)) \