M6 70 arch/mips/mm/uasm-mips.c [insn_cache] = {M6(spec3_op, 0, 0, 0, cache6_op), RS | RT | SIMM9}, M6 132 arch/mips/mm/uasm-mips.c [insn_ll] = {M6(spec3_op, 0, 0, 0, ll6_op), RS | RT | SIMM9}, M6 133 arch/mips/mm/uasm-mips.c [insn_lld] = {M6(spec3_op, 0, 0, 0, lld6_op), RS | RT | SIMM9}, M6 165 arch/mips/mm/uasm-mips.c [insn_pref] = {M6(spec3_op, 0, 0, 0, pref6_op), RS | RT | SIMM9}, M6 174 arch/mips/mm/uasm-mips.c [insn_sc] = {M6(spec3_op, 0, 0, 0, sc6_op), RS | RT | SIMM9}, M6 175 arch/mips/mm/uasm-mips.c [insn_scd] = {M6(spec3_op, 0, 0, 0, scd6_op), RS | RT | SIMM9},