M41T81REG_SC      155 arch/mips/sibyte/swarm/rtc_m41t81.c 	m41t81_write(M41T81REG_SC, tm.tm_sec);
M41T81REG_SC      196 arch/mips/sibyte/swarm/rtc_m41t81.c 		sec = m41t81_read(M41T81REG_SC);
M41T81REG_SC      198 arch/mips/sibyte/swarm/rtc_m41t81.c 		if (sec == m41t81_read(M41T81REG_SC)) break;
M41T81REG_SC      224 arch/mips/sibyte/swarm/rtc_m41t81.c 	tmp = m41t81_read(M41T81REG_SC);
M41T81REG_SC      225 arch/mips/sibyte/swarm/rtc_m41t81.c 	m41t81_write(M41T81REG_SC, tmp & 0x7f);
M41T81REG_SC      227 arch/mips/sibyte/swarm/rtc_m41t81.c 	return m41t81_read(M41T81REG_SC) != -1;