M1                109 arch/xtensa/variants/csp/include/variant/tie-asm.h 	rsr.M1	\at1		// MAC16 option
M1                176 arch/xtensa/variants/csp/include/variant/tie-asm.h 	wsr.M1	\at1		// MAC16 option
M1                 50 arch/xtensa/variants/dc232b/include/variant/tie-asm.h 	rsr	\at2, M1
M1                 93 arch/xtensa/variants/dc232b/include/variant/tie-asm.h 	wsr	\at2, M1
M1                106 arch/xtensa/variants/dc233c/include/variant/tie-asm.h 	rsr	\at1, M1			// MAC16 option
M1                171 arch/xtensa/variants/dc233c/include/variant/tie-asm.h 	wsr	\at1, M1			// MAC16 option
M1                 97 arch/xtensa/variants/de212/include/variant/tie-asm.h 	rsr.M1	\at1		// MAC16 option
M1                152 arch/xtensa/variants/de212/include/variant/tie-asm.h 	wsr.M1	\at1		// MAC16 option
M1                109 arch/xtensa/variants/test_kc705_be/include/variant/tie-asm.h 	rsr.M1	\at1		// MAC16 option
M1                176 arch/xtensa/variants/test_kc705_be/include/variant/tie-asm.h 	wsr.M1	\at1		// MAC16 option
M1                106 arch/xtensa/variants/test_kc705_hifi/include/variant/tie-asm.h 	rsr.M1	\at1		// MAC16 option
M1                173 arch/xtensa/variants/test_kc705_hifi/include/variant/tie-asm.h 	wsr.M1	\at1		// MAC16 option
M1                161 drivers/gpu/drm/nouveau/dispnv04/crtc.c 			 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
M1                164 drivers/gpu/drm/nouveau/dispnv04/crtc.c 			 pv->N1, pv->M1, pv->log2P);
M1                152 drivers/gpu/drm/nouveau/dispnv04/hw.c 			pllvals->M1 &= 0xf; /* only 4 bits */
M1                207 drivers/gpu/drm/nouveau/dispnv04/hw.c 	if (!pv->M1 || !pv->M2)
M1                210 drivers/gpu/drm/nouveau/dispnv04/hw.c 	return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P;
M1                270 drivers/gpu/drm/nouveau/dispnv04/hw.c 	if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m &&
M1                278 drivers/gpu/drm/nouveau/dispnv04/hw.c 	pv.M1 = pll_lim.vco1.max_m;
M1                  9 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h 			uint8_t N1, M1, N2, M2;
M1                 11 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h 			uint8_t M1, N1, M2, N2;
M1                 57 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 	int N1, M1;
M1                 71 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 	M1 = (coef & 0x000000ff);
M1                 72 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 	if ((ctrl & 0x80000000) && M1) {
M1                 73 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c 		clock = ref * N1 / M1;
M1                 35 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c 	int N1, M1, N2, M2, P;
M1                 36 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c 	int ret = nv04_pll_calc(&clock->subdev, info, clk, &N1, &M1, &N2, &M2, &P);
M1                 40 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c 		pv->M1 = M1;
M1                 64 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 	int M1 = (coef & 0x000000ff) >> 0;
M1                 68 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 	if ((ctrl & 0x80000000) && M1) {
M1                 69 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 		khz = ref * N1 / M1;
M1                125 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 		  int *N1, int *M1, int *N2, int *M2, int *log2P)
M1                138 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 	ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P);
M1                151 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 	int N1, M1, N2, M2, log2P;
M1                156 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 				&N1, &M1, &N2, &M2, &log2P);
M1                162 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 		clk->npll_coef = (N1 << 8) | M1;
M1                165 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 		clk->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
M1                171 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 					&N1, &M1, NULL, NULL, &log2P);
M1                175 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c 		clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1;
M1                166 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	int N1, N2, M1, M2;
M1                177 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	M1 = (coef & 0x000000ff);
M1                178 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 	if ((ctrl & 0x80000000) && M1) {
M1                179 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c 		freq = ref * N1 / M1;
M1                  9 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h 		  int *N1, int *M1, int *N2, int *M2, int *P);
M1                151 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 	int M1, N1, M2, N2, log2P;
M1                164 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 	for (M1 = minM1; M1 <= maxM1; M1++) {
M1                165 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 		if (crystal/M1 < minU1)
M1                167 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 		if (crystal/M1 > maxU1)
M1                171 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 			calcclk1 = crystal * N1 / M1;
M1                212 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 					*pM1 = M1;
M1                228 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 	      int *N1, int *M1, int *N2, int *M2, int *P)
M1                233 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 		ret = getMNP_single(subdev, info, freq, N1, M1, P);
M1                239 drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c 		ret = getMNP_double(subdev, info, freq, N1, M1, N2, M2, P);
M1                164 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c 	if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))
M1                363 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c 	int N1, M1, N2, M2, P;
M1                370 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c 	ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P);
M1                376 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c 	pv.M1 = M1;
M1                 41 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c 	int N1, M1, N2, M2, P;
M1                 50 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c 	ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P);
M1                 60 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c 		nvkm_mask(device, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1);
M1                 69 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c 		nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1);
M1                 73 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c 		nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1);
M1                143 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c 	int N1, M1, P;
M1                216 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c 				     &N1, NULL, &M1, &P);
M1                225 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c 		ram_wr32(fuc, 0x10fe24, (P << 16) | (N1 << 8) | M1);
M1                231 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c 				     &N1, NULL, &M1, &P);
M1                238 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c 		ram_wr32(fuc, 0x132004, (P << 16) | (N1 << 8) | M1);
M1                133 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 	int N1, fN1, M1, P1;
M1                161 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 	const u32 rcoef = ((  ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
M1                703 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 	const u32 rcoef = ((  ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
M1                989 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 		int *N1, int *fN1, int *M1, int *P1,
M1                995 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 	*M1 = 1;
M1               1033 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 	*fN1 = (u16)((((best_err / *N2 * *P2) * (*P1 * *M1)) << 13) / crystal);
M1               1066 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 				&ram->N1, &ram->fN1, &ram->M1, &ram->P1,
M1               1078 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c 				     &ram->fN1, &ram->M1, &ram->P1);
M1                 40 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c 	int N1, M1, N2, M2;
M1                 49 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c 	ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P);
M1                 57 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c 		ram->coef  = (N1 << 8) | M1;
M1                 60 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c 		ram->coef  = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
M1                231 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	int N1, M1, N2, M2, P;
M1                332 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 				    &N1, &M1, &N2, &M2, &P);
M1                356 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c 	ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1);
M1               1520 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c SIG_EXPR_LIST_DECL_SINGLE(M1, GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1));
M1               1521 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c SIG_EXPR_LIST_DECL_SINGLE(M1, ADC9, ADC9);
M1               1522 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c PIN_DECL_(M1, SIG_EXPR_LIST_PTR(M1, GPIOX1), SIG_EXPR_LIST_PTR(M1, ADC9));
M1               1523 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c FUNC_GROUP_DECL(ADC9, M1);
M1               2057 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c 	ASPEED_PINCTRL_PIN(M1),
M1               2510 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c 	{ PIN_CONFIG_BIAS_PULL_DOWN, { M1,  M1  }, SCUA8, 13 },
M1               2511 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c 	{ PIN_CONFIG_BIAS_DISABLE,   { M1,  M1  }, SCUA8, 13 },