LVL_1_INST         45 arch/x86/kernel/cpu/cacheinfo.c 	{ 0x06, LVL_1_INST, 8 },	/* 4-way set assoc, 32 byte line size */
LVL_1_INST         46 arch/x86/kernel/cpu/cacheinfo.c 	{ 0x08, LVL_1_INST, 16 },	/* 4-way set assoc, 32 byte line size */
LVL_1_INST         47 arch/x86/kernel/cpu/cacheinfo.c 	{ 0x09, LVL_1_INST, 32 },	/* 4-way set assoc, 64 byte line size */
LVL_1_INST         58 arch/x86/kernel/cpu/cacheinfo.c 	{ 0x30, LVL_1_INST, 32 },	/* 8-way set assoc, 64 byte line size */
LVL_1_INST        813 arch/x86/kernel/cpu/cacheinfo.c 						case LVL_1_INST: