LVDS              282 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.saveLVDS = REG_READ(LVDS);
LVDS              350 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(LVDS, regs->cdv.saveLVDS);
LVDS              708 drivers/gpu/drm/gma500/cdv_intel_display.c 		if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
LVDS              739 drivers/gpu/drm/gma500/cdv_intel_display.c 		u32 lvds = REG_READ(LVDS);
LVDS              758 drivers/gpu/drm/gma500/cdv_intel_display.c 		REG_WRITE(LVDS, lvds);
LVDS              759 drivers/gpu/drm/gma500/cdv_intel_display.c 		REG_READ(LVDS);
LVDS              858 drivers/gpu/drm/gma500/cdv_intel_display.c 		is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
LVDS              707 drivers/gpu/drm/gma500/cdv_intel_lvds.c 	lvds = REG_READ(LVDS);
LVDS              710 drivers/gpu/drm/gma500/gma_display.c 	    (REG_READ(LVDS) & LVDS_PORT_EN) != 0) {
LVDS              717 drivers/gpu/drm/gma500/gma_display.c 		if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
LVDS              238 drivers/gpu/drm/gma500/oaktrail_device.c 	regs->psb.saveLVDS = PSB_RVDC32(LVDS);
LVDS              362 drivers/gpu/drm/gma500/oaktrail_device.c 		PSB_WVDC32(regs->psb.saveLVDS, LVDS); /*port 61180h*/
LVDS              100 drivers/gpu/drm/gma500/oaktrail_lvds.c 	lvds_port = (REG_READ(LVDS) &
LVDS              110 drivers/gpu/drm/gma500/oaktrail_lvds.c 	REG_WRITE(LVDS, lvds_port);
LVDS              224 drivers/gpu/drm/gma500/psb_intel_display.c 		u32 lvds = REG_READ(LVDS);
LVDS              244 drivers/gpu/drm/gma500/psb_intel_display.c 		REG_WRITE(LVDS, lvds);
LVDS              245 drivers/gpu/drm/gma500/psb_intel_display.c 		REG_READ(LVDS);
LVDS              316 drivers/gpu/drm/gma500/psb_intel_display.c 		is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
LVDS              263 drivers/gpu/drm/gma500/psb_intel_lvds.c 	lvds_priv->saveLVDS = REG_READ(LVDS);
LVDS              316 drivers/gpu/drm/gma500/psb_intel_lvds.c 	REG_WRITE(LVDS, lvds_priv->saveLVDS);
LVDS              772 drivers/gpu/drm/gma500/psb_intel_lvds.c 	lvds = REG_READ(LVDS);
LVDS             1229 drivers/gpu/drm/i915/display/intel_display.c 		intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
LVDS             11338 drivers/gpu/drm/i915/display/intel_display.c 		u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
LVDS             11991 drivers/gpu/drm/i915/display/intel_display.c 	OUTPUT_TYPE(LVDS),
LVDS              843 drivers/gpu/drm/i915/display/intel_lvds.c 		lvds_reg = LVDS;
LVDS              220 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c 		if (ior->asy.proto == LVDS) {
LVDS              452 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c 	if (ior->type == SOR && ior->asy.proto == LVDS) {
LVDS               67 drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c 		case DCB_OUTPUT_LVDS  : *type = SOR; return LVDS;
LVDS              245 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c 	case 0: state->proto = LVDS; state->link = 1; break;
LVDS              144 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c 	case 0: state->proto = LVDS; state->link = 1; break;
LVDS               66 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c 	case 0: state->proto = LVDS; state->link = 1; break;
LVDS               75 drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c 	case 0: state->proto = LVDS; state->link = 1; break;
LVDS              286 drivers/video/fbdev/intelfb/intelfbhw.c 	if (INREG(LVDS) & PORT_ENABLE)
LVDS              582 drivers/video/fbdev/intelfb/intelfbhw.c 	hw->lvds = INREG(LVDS);
LVDS              637 drivers/video/fbdev/nvidia/nv_setup.c 	par->LVDS = 0;
LVDS              641 drivers/video/fbdev/nvidia/nv_setup.c 			par->LVDS = 1;
LVDS              642 drivers/video/fbdev/nvidia/nv_setup.c 		printk("nvidiafb: Panel is %s\n", par->LVDS ? "LVDS" : "TMDS");
LVDS              135 drivers/video/fbdev/nvidia/nv_type.h 	int LVDS;