LSP1_UART5_CLK 820 drivers/clk/zte/clk-zx296718.c MUX(0, "uart5_wclk_mux", lsp1_wclk_common_p, LSP1_UART5_CLK, 4, 1), LSP1_UART5_CLK 838 drivers/clk/zte/clk-zx296718.c GATE(LSP1_UART5_WCLK, "lsp1_uart5_wclk", "uart5_wclk_mux", LSP1_UART5_CLK, 1, CLK_SET_RATE_PARENT, 0),