LSP1_PWM_CLK      821 drivers/clk/zte/clk-zx296718.c 	MUX(0, "pwm_wclk_mux",   lsp1_wclk_common_p, LSP1_PWM_CLK,   4, 1),
LSP1_PWM_CLK      830 drivers/clk/zte/clk-zx296718.c 	DIV_T(0, "pwm_div",  "pwm_wclk_mux",  LSP1_PWM_CLK,  12, 4, CLK_SET_RATE_PARENT, common_div_table),
LSP1_PWM_CLK      839 drivers/clk/zte/clk-zx296718.c 	GATE(LSP1_PWM_WCLK,   "lsp1_pwm_wclk",   "pwm_div",        LSP1_PWM_CLK,   1, CLK_SET_RATE_PARENT, 0),
LSP1_PWM_CLK      840 drivers/clk/zte/clk-zx296718.c 	GATE(LSP1_PWM_PCLK,   "lsp1_pwm_pclk",   "lsp1_pclk",      LSP1_PWM_CLK,   0, 0,		   0),