LSP0_UART2_CLK    710 drivers/clk/zte/clk-zx296718.c 	MUX(0, "uart2_wclk_mux",  lsp0_wclk_common_p, LSP0_UART2_CLK,  4, 1),
LSP0_UART2_CLK    725 drivers/clk/zte/clk-zx296718.c 	GATE(LSP0_UART2_WCLK,  "uart2_wclk",  "uart2_wclk_mux",  LSP0_UART2_CLK,  1, CLK_SET_RATE_PARENT, 0),