LSP0_UART1_CLK    709 drivers/clk/zte/clk-zx296718.c 	MUX(0, "uart1_wclk_mux",  lsp0_wclk_common_p, LSP0_UART1_CLK,  4, 1),
LSP0_UART1_CLK    724 drivers/clk/zte/clk-zx296718.c 	GATE(LSP0_UART1_WCLK,  "uart1_wclk",  "uart1_wclk_mux",  LSP0_UART1_CLK,  1, CLK_SET_RATE_PARENT, 0),