LSP0_TIMER4_CLK   706 drivers/clk/zte/clk-zx296718.c 	MUX(0, "timer4_wclk_mux", lsp0_wclk_timer4_p, LSP0_TIMER4_CLK, 4, 1),
LSP0_TIMER4_CLK   721 drivers/clk/zte/clk-zx296718.c 	GATE(LSP0_TIMER4_WCLK, "timer4_wclk", "timer4_wclk_mux", LSP0_TIMER4_CLK, 1, CLK_SET_RATE_PARENT, 0),
LSP0_TIMER4_CLK   736 drivers/clk/zte/clk-zx296718.c 	DIV_T(0, "timer4_div", "lsp0_24m", LSP0_TIMER4_CLK,  12, 4, 0, common_even_div_table),