LE_SF 132 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_ENABLE, mask_sh),\ LE_SF 133 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\ LE_SF 134 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DIG0_DIG_BE_CNTL, DIG_MODE, mask_sh),\ LE_SF 135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\ LE_SF 136 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ LE_SF 137 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\ LE_SF 138 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\ LE_SF 139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\ LE_SF 140 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\ LE_SF 141 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\ LE_SF 142 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\ LE_SF 143 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\ LE_SF 144 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\ LE_SF 145 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\ LE_SF 146 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\ LE_SF 147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\ LE_SF 148 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\ LE_SF 149 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\ LE_SF 150 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\ LE_SF 151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\ LE_SF 152 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\ LE_SF 153 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\ LE_SF 154 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\ LE_SF 155 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\ LE_SF 156 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\ LE_SF 157 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\ LE_SF 158 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\ LE_SF 159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\ LE_SF 160 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\ LE_SF 161 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\ LE_SF 162 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\ LE_SF 163 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\ LE_SF 164 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\ LE_SF 165 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\ LE_SF 166 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\ LE_SF 167 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\ LE_SF 168 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\ LE_SF 169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\ LE_SF 170 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\ LE_SF 171 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\ LE_SF 172 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\ LE_SF 173 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\ LE_SF 174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\ LE_SF 175 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\ LE_SF 176 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\ LE_SF 177 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\ LE_SF 178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\ LE_SF 179 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh) LE_SF 36 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(UNIPHYA_CHANNEL_XBAR_CNTL, UNIPHY_LINK_ENABLE, mask_sh) LE_SF 40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\ LE_SF 41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\ LE_SF 42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\ LE_SF 43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE0EN, mask_sh),\ LE_SF 44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE1EN, mask_sh),\ LE_SF 45 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE2EN, mask_sh),\ LE_SF 46 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE3EN, mask_sh),\ LE_SF 47 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DIG0_DIG_LANE_ENABLE, DIG_CLK_EN, mask_sh),\ LE_SF 48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ LE_SF 50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\ LE_SF 51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\ LE_SF 52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\ LE_SF 53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\ LE_SF 54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\ LE_SF 55 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\ LE_SF 56 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\ LE_SF 57 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \ LE_SF 58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\ LE_SF 59 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\ LE_SF 60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh)