LCPLL_CTL 409 drivers/gpu/drm/i915/display/intel_cdclk.c u32 lcpll = I915_READ(LCPLL_CTL); LCPLL_CTL 689 drivers/gpu/drm/i915/display/intel_cdclk.c u32 lcpll = I915_READ(LCPLL_CTL); LCPLL_CTL 721 drivers/gpu/drm/i915/display/intel_cdclk.c if (WARN((I915_READ(LCPLL_CTL) & LCPLL_CTL 736 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(LCPLL_CTL); LCPLL_CTL 738 drivers/gpu/drm/i915/display/intel_cdclk.c I915_WRITE(LCPLL_CTL, val); LCPLL_CTL 744 drivers/gpu/drm/i915/display/intel_cdclk.c if (wait_for_us(I915_READ(LCPLL_CTL) & LCPLL_CTL 748 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(LCPLL_CTL); LCPLL_CTL 769 drivers/gpu/drm/i915/display/intel_cdclk.c I915_WRITE(LCPLL_CTL, val); LCPLL_CTL 771 drivers/gpu/drm/i915/display/intel_cdclk.c val = I915_READ(LCPLL_CTL); LCPLL_CTL 773 drivers/gpu/drm/i915/display/intel_cdclk.c I915_WRITE(LCPLL_CTL, val); LCPLL_CTL 775 drivers/gpu/drm/i915/display/intel_cdclk.c if (wait_for_us((I915_READ(LCPLL_CTL) & LCPLL_CTL 4226 drivers/gpu/drm/i915/display/intel_display_power.c u32 val = I915_READ(LCPLL_CTL); LCPLL_CTL 4319 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(LCPLL_CTL); LCPLL_CTL 4323 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(LCPLL_CTL, val); LCPLL_CTL 4325 drivers/gpu/drm/i915/display/intel_display_power.c if (wait_for_us(I915_READ(LCPLL_CTL) & LCPLL_CTL 4329 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(LCPLL_CTL); LCPLL_CTL 4333 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(LCPLL_CTL, val); LCPLL_CTL 4334 drivers/gpu/drm/i915/display/intel_display_power.c POSTING_READ(LCPLL_CTL); LCPLL_CTL 4336 drivers/gpu/drm/i915/display/intel_display_power.c if (intel_de_wait_for_clear(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 1)) LCPLL_CTL 4349 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(LCPLL_CTL); LCPLL_CTL 4351 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(LCPLL_CTL, val); LCPLL_CTL 4352 drivers/gpu/drm/i915/display/intel_display_power.c POSTING_READ(LCPLL_CTL); LCPLL_CTL 4364 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(LCPLL_CTL); LCPLL_CTL 4378 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(LCPLL_CTL, val); LCPLL_CTL 4379 drivers/gpu/drm/i915/display/intel_display_power.c POSTING_READ(LCPLL_CTL); LCPLL_CTL 4387 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(LCPLL_CTL); LCPLL_CTL 4389 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(LCPLL_CTL, val); LCPLL_CTL 4391 drivers/gpu/drm/i915/display/intel_display_power.c if (intel_de_wait_for_set(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 5)) LCPLL_CTL 4395 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(LCPLL_CTL); LCPLL_CTL 4397 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(LCPLL_CTL, val); LCPLL_CTL 4399 drivers/gpu/drm/i915/display/intel_display_power.c if (wait_for_us((I915_READ(LCPLL_CTL) & LCPLL_CTL 2305 drivers/gpu/drm/i915/gvt/handlers.c MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);