LCPLL1_CTL        830 drivers/gpu/drm/i915/display/intel_cdclk.c 	val = I915_READ(LCPLL1_CTL);
LCPLL1_CTL        970 drivers/gpu/drm/i915/display/intel_cdclk.c 	I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
LCPLL1_CTL        972 drivers/gpu/drm/i915/display/intel_cdclk.c 	if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
LCPLL1_CTL        983 drivers/gpu/drm/i915/display/intel_cdclk.c 	I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
LCPLL1_CTL        984 drivers/gpu/drm/i915/display/intel_cdclk.c 	if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
LCPLL1_CTL        961 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		.ctl = LCPLL1_CTL,
LCPLL1_CTL        222 drivers/gpu/drm/i915/gvt/display.c 		vgpu_vreg_t(vgpu, LCPLL1_CTL) =
LCPLL1_CTL       2896 drivers/gpu/drm/i915/gvt/handlers.c 	MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);