LCD_SPU_DMA_CTRL1  390 drivers/gpu/drm/armada/armada_crtc.c 	armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
LCD_SPU_DMA_CTRL1  940 drivers/gpu/drm/armada/armada_crtc.c 	writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
LCD_SPU_DMA_CTRL1  203 drivers/gpu/drm/armada/armada_overlay.c 				     LCD_SPU_DMA_CTRL1);
LCD_SPU_DMA_CTRL1  128 drivers/video/fbdev/mmp/hw/mmp_ctrl.h 				LCD_PN2_CTRL1) : LCD_SPU_DMA_CTRL1)
LCD_SPU_DMA_CTRL1  338 drivers/video/fbdev/pxa168fb.c 	x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL1);
LCD_SPU_DMA_CTRL1  348 drivers/video/fbdev/pxa168fb.c 	writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL1);