LCD_SPU_DMA_CTRL0  164 drivers/gpu/drm/armada/armada_crtc.c 			       base + LCD_SPU_DMA_CTRL0);
LCD_SPU_DMA_CTRL0  166 drivers/gpu/drm/armada/armada_crtc.c 		armada_updatel(0, CFG_GAMMA_ENA, base + LCD_SPU_DMA_CTRL0);
LCD_SPU_DMA_CTRL0  287 drivers/gpu/drm/armada/armada_crtc.c 				       base + LCD_SPU_DMA_CTRL0);
LCD_SPU_DMA_CTRL0  639 drivers/gpu/drm/armada/armada_crtc.c 		armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
LCD_SPU_DMA_CTRL0  662 drivers/gpu/drm/armada/armada_crtc.c 		armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
LCD_SPU_DMA_CTRL0  957 drivers/gpu/drm/armada/armada_crtc.c 	armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
LCD_SPU_DMA_CTRL0  169 drivers/gpu/drm/armada/armada_overlay.c 				     LCD_SPU_DMA_CTRL0);
LCD_SPU_DMA_CTRL0  235 drivers/gpu/drm/armada/armada_overlay.c 	armada_reg_queue_mod(regs, idx, 0, CFG_DMA_ENA, LCD_SPU_DMA_CTRL0);
LCD_SPU_DMA_CTRL0  239 drivers/gpu/drm/armada/armada_plane.c 				     LCD_SPU_DMA_CTRL0);
LCD_SPU_DMA_CTRL0  265 drivers/gpu/drm/armada/armada_plane.c 	armada_reg_queue_mod(regs, idx, 0, CFG_GRA_ENA, LCD_SPU_DMA_CTRL0);
LCD_SPU_DMA_CTRL0  126 drivers/video/fbdev/mmp/hw/mmp_ctrl.h 				LCD_PN2_CTRL0) : LCD_SPU_DMA_CTRL0)
LCD_SPU_DMA_CTRL0  301 drivers/video/fbdev/pxa168fb.c 	x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0);
LCD_SPU_DMA_CTRL0  326 drivers/video/fbdev/pxa168fb.c 	writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0);
LCD_SPU_DMA_CTRL0  789 drivers/video/fbdev/pxa168fb.c 	data = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0);
LCD_SPU_DMA_CTRL0  791 drivers/video/fbdev/pxa168fb.c 	writel(data, fbi->reg_base + LCD_SPU_DMA_CTRL0);