LCDC_RASTER_TIMING_2_REG  327 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 	reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
LCDC_RASTER_TIMING_2_REG  342 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 	tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
LCDC_RASTER_TIMING_2_REG  365 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 			tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
LCDC_RASTER_TIMING_2_REG  368 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 			tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
LCDC_RASTER_TIMING_2_REG  403 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
LCDC_RASTER_TIMING_2_REG  405 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
LCDC_RASTER_TIMING_2_REG  408 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
LCDC_RASTER_TIMING_2_REG  410 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
LCDC_RASTER_TIMING_2_REG  413 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
LCDC_RASTER_TIMING_2_REG  415 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
LCDC_RASTER_TIMING_2_REG  418 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
LCDC_RASTER_TIMING_2_REG  420 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
LCDC_RASTER_TIMING_2_REG  423 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
LCDC_RASTER_TIMING_2_REG  425 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
LCDC_RASTER_TIMING_2_REG  434 drivers/gpu/drm/tilcdc/tilcdc_drv.c 		REG(1, true,  LCDC_RASTER_TIMING_2_REG),