LCDC_RASTER_CTRL_REG  113 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 	tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,
LCDC_RASTER_CTRL_REG  119 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
LCDC_RASTER_CTRL_REG  125 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 	tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
LCDC_RASTER_CTRL_REG  133 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 	tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
LCDC_RASTER_CTRL_REG  135 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
LCDC_RASTER_CTRL_REG  147 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
LCDC_RASTER_CTRL_REG  166 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
LCDC_RASTER_CTRL_REG  374 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 	reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
LCDC_RASTER_CTRL_REG  400 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 	tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
LCDC_RASTER_CTRL_REG  428 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
LCDC_RASTER_CTRL_REG  430 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
LCDC_RASTER_CTRL_REG  465 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 	tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,
LCDC_RASTER_CTRL_REG  477 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 	tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
LCDC_RASTER_CTRL_REG  506 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 	tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
LCDC_RASTER_CTRL_REG  686 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 	if (tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & LCDC_RASTER_ENABLE) {
LCDC_RASTER_CTRL_REG  692 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 		tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
LCDC_RASTER_CTRL_REG  922 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 			tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
LCDC_RASTER_CTRL_REG  934 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 			reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG);
LCDC_RASTER_CTRL_REG  936 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 				tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
LCDC_RASTER_CTRL_REG  938 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 				tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
LCDC_RASTER_CTRL_REG  961 drivers/gpu/drm/tilcdc/tilcdc_crtc.c 			tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
LCDC_RASTER_CTRL_REG  431 drivers/gpu/drm/tilcdc/tilcdc_drv.c 		REG(1, true,  LCDC_RASTER_CTRL_REG),