LCDC               60 arch/sh/kernel/cpu/sh2a/setup-sh7203.c 	INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141),
LCDC              142 arch/sh/kernel/cpu/sh2a/setup-sh7203.c 	{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } },
LCDC               61 arch/sh/kernel/cpu/sh3/setup-sh770x.c 	INTC_VECT(LCDC, 0x9a0),
LCDC               82 arch/sh/kernel/cpu/sh3/setup-sh770x.c 	{ 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
LCDC              246 arch/sh/kernel/cpu/sh3/setup-sh7720.c 	INTC_VECT(DMAC1, 0x860),      INTC_VECT(LCDC, 0x900),
LCDC              270 arch/sh/kernel/cpu/sh3/setup-sh7720.c 	{ 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },
LCDC               55 arch/sh/kernel/cpu/sh4/setup-sh7760.c 	INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20),
LCDC               89 arch/sh/kernel/cpu/sh4/setup-sh7760.c 	    SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
LCDC              110 arch/sh/kernel/cpu/sh4/setup-sh7760.c 	{ 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,
LCDC              363 arch/sh/kernel/cpu/sh4a/setup-sh7343.c 	INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
LCDC              387 arch/sh/kernel/cpu/sh4a/setup-sh7343.c 	  { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
LCDC              409 arch/sh/kernel/cpu/sh4a/setup-sh7343.c 	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
LCDC              301 arch/sh/kernel/cpu/sh4a/setup-sh7366.c 	INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580),
LCDC              324 arch/sh/kernel/cpu/sh4a/setup-sh7366.c 	  { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } },
LCDC              346 arch/sh/kernel/cpu/sh4a/setup-sh7366.c 	{ 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } },
LCDC              576 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 	INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
LCDC              601 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 	  { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
LCDC              623 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
LCDC              992 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 	INTC_VECT(LCDC, 0xF40),
LCDC             1028 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 	    JPU, 0, 0, LCDC } },
LCDC             1058 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },
LCDC              414 arch/sh/kernel/cpu/sh4a/setup-sh7734.c 	INTC_VECT(LCDC, 0xC40),
LCDC              450 arch/sh/kernel/cpu/sh4a/setup-sh7734.c 	INTC_GROUP(LCDC_M, LCDC, MIMLB), /* 13 */
LCDC              508 arch/sh/kernel/cpu/sh4a/setup-sh7734.c 		{ SCIF0, SCIF3, HSCIF, LCDC } },
LCDC              258 arch/sh/kernel/cpu/sh4a/setup-sh7763.c 	INTC_VECT(LCDC, 0x620),
LCDC              310 arch/sh/kernel/cpu/sh4a/setup-sh7763.c 	    LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } },
LCDC              326 arch/sh/kernel/cpu/sh4a/setup-sh7763.c 	{ 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } },