L1_CACHE_SHIFT     16 arch/arc/include/asm/cache.h #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
L1_CACHE_SHIFT     18 arch/arc/lib/memset-archs.S #if L1_CACHE_SHIFT == 6
L1_CACHE_SHIFT      9 arch/arm/include/asm/cache.h #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
L1_CACHE_SHIFT     31 arch/arm64/include/asm/cache.h #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
L1_CACHE_SHIFT     36 arch/c6x/include/asm/cache.h #define L1_CACHE_BYTES        (1 << L1_CACHE_SHIFT)
L1_CACHE_SHIFT      9 arch/csky/include/asm/cache.h #define L1_CACHE_BYTES	(1 << L1_CACHE_SHIFT)
L1_CACHE_SHIFT      7 arch/h8300/include/asm/cache.h #define        L1_CACHE_BYTES  (1 << L1_CACHE_SHIFT)
L1_CACHE_SHIFT     13 arch/hexagon/include/asm/cache.h #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
L1_CACHE_SHIFT     13 arch/ia64/include/asm/cache.h #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
L1_CACHE_SHIFT     16 arch/ia64/include/asm/cache.h # define SMP_CACHE_SHIFT	L1_CACHE_SHIFT
L1_CACHE_SHIFT     10 arch/m68k/include/asm/cache.h #define        L1_CACHE_BYTES  (1<< L1_CACHE_SHIFT)
L1_CACHE_SHIFT     20 arch/microblaze/include/asm/cache.h #define L1_CACHE_BYTES	(1 << L1_CACHE_SHIFT)
L1_CACHE_SHIFT     15 arch/mips/include/asm/cache.h #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
L1_CACHE_SHIFT     30 arch/powerpc/include/asm/cache.h #define	L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
L1_CACHE_SHIFT     80 arch/powerpc/include/asm/cache.h 	return L1_CACHE_SHIFT;
L1_CACHE_SHIFT     90 arch/powerpc/include/asm/cache.h 	return L1_CACHE_SHIFT;
L1_CACHE_SHIFT    733 arch/powerpc/kernel/vdso.c 	vdso_data->dcache_log_block_size = L1_CACHE_SHIFT;
L1_CACHE_SHIFT    735 arch/powerpc/kernel/vdso.c 	vdso_data->icache_log_block_size = L1_CACHE_SHIFT;
L1_CACHE_SHIFT     12 arch/riscv/include/asm/cache.h #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
L1_CACHE_SHIFT     16 arch/sh/include/asm/cache.h #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
L1_CACHE_SHIFT     16 arch/um/include/asm/cache.h #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
L1_CACHE_SHIFT     13 arch/unicore32/include/asm/cache.h #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
L1_CACHE_SHIFT      9 arch/x86/include/asm/cache.h #define L1_CACHE_BYTES	(1 << L1_CACHE_SHIFT)
L1_CACHE_SHIFT   2420 drivers/acpi/nfit/core.c 	cmd = (dpa >> L1_CACHE_SHIFT) & BCW_OFFSET_MASK;
L1_CACHE_SHIFT   2421 drivers/acpi/nfit/core.c 	len = len >> L1_CACHE_SHIFT;
L1_CACHE_SHIFT   1414 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define BNX2X_RX_ALIGN_SHIFT		max(6, min(8, L1_CACHE_SHIFT))
L1_CACHE_SHIFT   5038 drivers/net/ethernet/broadcom/cnic.c 	data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
L1_CACHE_SHIFT    244 drivers/net/ethernet/qlogic/qede/qede.h #define QEDE_RX_ALIGN_SHIFT		max(6, min(8, L1_CACHE_SHIFT))
L1_CACHE_SHIFT    244 drivers/net/macvlan.c 	return (u32)(((unsigned long)vlan) >> L1_CACHE_SHIFT);
L1_CACHE_SHIFT    642 drivers/parisc/sba_iommu.c 				entries_per_cacheline = L1_CACHE_SHIFT - 3;
L1_CACHE_SHIFT     62 fs/dcookies.c  	return (dcookie >> L1_CACHE_SHIFT) & (hash_size - 1);
L1_CACHE_SHIFT    268 fs/quota/dquot.c 	tmp = (((unsigned long)sb>>L1_CACHE_SHIFT) ^ id) * (MAXQUOTAS - type);
L1_CACHE_SHIFT   2810 fs/reiserfs/reiserfs.h 	(((unsigned long)sb>>L1_CACHE_SHIFT) ^ \
L1_CACHE_SHIFT     11 include/asm-generic/cache.h #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
L1_CACHE_SHIFT     66 include/linux/cache.h #define INTERNODE_CACHE_SHIFT L1_CACHE_SHIFT
L1_CACHE_SHIFT    456 kernel/dma/debug.c #define CACHELINE_PER_PAGE_SHIFT (PAGE_SHIFT - L1_CACHE_SHIFT)
L1_CACHE_SHIFT    462 kernel/dma/debug.c 		(entry->offset >> L1_CACHE_SHIFT);
L1_CACHE_SHIFT     40 lib/atomic64.c 	addr >>= L1_CACHE_SHIFT;