L1                 78 arch/alpha/boot/bootp.c 	pcb_va->ptbr = L1[1] >> 32;
L1                126 arch/alpha/boot/bootpz.c 	pcb_va->ptbr = L1[1] >> 32;
L1                 72 arch/alpha/boot/main.c 	pcb_va->ptbr = L1[1] >> 32;
L1                164 arch/powerpc/perf/isa207-common.c 		ret = PH(LVL, L1);
L1                196 arch/powerpc/perf/isa207-common.c 		ret = PM(LVL, L1);
L1                133 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(L1-dcache-load-misses,		PM_LD_MISS_L1);
L1                134 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(L1-dcache-loads,		PM_LD_REF_L1);
L1                136 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(L1-dcache-prefetches,		PM_L1_PREF);
L1                137 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(L1-dcache-store-misses,	PM_ST_MISS_L1);
L1                138 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(L1-icache-load-misses,		PM_L1_ICACHE_MISS);
L1                139 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(L1-icache-loads,		PM_INST_FROM_L1);
L1                140 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(L1-icache-prefetches,		PM_IC_PREF_WRITE);
L1                163 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(L1-dcache-load-misses,		PM_LD_MISS_L1_FIN);
L1                164 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(L1-dcache-loads,		PM_LD_REF_L1);
L1                165 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(L1-dcache-prefetches,		PM_L1_PREF);
L1                166 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(L1-dcache-store-misses,	PM_ST_MISS_L1);
L1                167 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(L1-icache-load-misses,		PM_L1_ICACHE_MISS);
L1                168 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(L1-icache-loads,		PM_INST_FROM_L1);
L1                169 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(L1-icache-prefetches,		PM_IC_PREF_WRITE);
L1                221 arch/sparc/net/bpf_jit_comp_64.c 	[BPF_REG_7] = L1,
L1                 63 arch/x86/events/intel/ds.c 	OP_LH | P(LVL, L1)  | LEVEL(L1) | P(SNOOP, NONE),  /* 0x01: L1 local */
L1                102 arch/x86/events/intel/ds.c 	u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
L1                192 arch/x86/events/intel/ds.c 		val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
L1                126 drivers/cpufreq/s5pv210-cpufreq.c 	{0, L1, 800*1000},
L1                149 drivers/cpufreq/s5pv210-cpufreq.c 	[L1] = {
L1               1490 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c SIG_EXPR_LIST_DECL_SINGLE(L1, GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28));
L1               1491 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c SIG_EXPR_LIST_DECL_SINGLE(L1, ADC4, ADC4);
L1               1492 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c PIN_DECL_(L1, SIG_EXPR_LIST_PTR(L1, GPIOW4), SIG_EXPR_LIST_PTR(L1, ADC4));
L1               1493 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c FUNC_GROUP_DECL(ADC4, L1);
L1               2047 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c 	ASPEED_PINCTRL_PIN(L1),
L1               2500 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c 	{ PIN_CONFIG_BIAS_PULL_DOWN, { L1,  L1  }, SCUA8, 8 },
L1               2501 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c 	{ PIN_CONFIG_BIAS_DISABLE,   { L1,  L1  }, SCUA8, 8 },
L1                658 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c SIG_EXPR_LIST_DECL_SINGLE(L1, SCL6, I2C6, I2C6_DESC);
L1                659 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c PIN_DECL_1(L1, GPIOK2, SCL6);
L1                665 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c FUNC_GROUP_DECL(I2C6, L1, N2);
L1               2047 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c 	ASPEED_PINCTRL_PIN(L1),
L1                164 security/apparmor/include/label.h #define next_comb(I, L1, L2)						\
L1                175 security/apparmor/include/label.h #define label_for_each_comb(I, L1, L2, P1, P2)				\
L1                177 security/apparmor/include/label.h 	((P1) = (L1)->vec[(I).i]) && ((P2) = (L2)->vec[(I).j]);		\
L1                178 security/apparmor/include/label.h 	(I) = next_comb(I, L1, L2))
L1                180 security/apparmor/include/label.h #define fn_for_each_comb(L1, L2, P1, P2, FN)				\
L1                184 security/apparmor/include/label.h 	label_for_each_comb(i, (L1), (L2), (P1), (P2)) {		\
L1                244 security/apparmor/include/label.h #define fn_for_each2_XXX(L1, L2, P, FN, ...)				\
L1                248 security/apparmor/include/label.h 	label_for_each ## __VA_ARGS__(i, (L1), (L2), (P)) {		\
L1                254 security/apparmor/include/label.h #define fn_for_each_in_merge(L1, L2, P, FN)				\
L1                255 security/apparmor/include/label.h 	fn_for_each2_XXX((L1), (L2), P, FN, _in_merge)
L1                256 security/apparmor/include/label.h #define fn_for_each_not_in_set(L1, L2, P, FN)				\
L1                257 security/apparmor/include/label.h 	fn_for_each2_XXX((L1), (L2), P, FN, _not_in_set)
L1                122 security/apparmor/include/perms.h #define xcheck_ns_labels(L1, L2, FN, args...)			\
L1                125 security/apparmor/include/perms.h 	fn_for_each((L1), __p1, FN(__p1, (L2), args));		\
L1                129 security/apparmor/include/perms.h #define xcheck_labels_profiles(L1, L2, FN, args...)		\
L1                130 security/apparmor/include/perms.h 	xcheck_ns_labels((L1), (L2), xcheck_ns_profile_label, (FN), args)
L1                132 security/apparmor/include/perms.h #define xcheck_labels(L1, L2, P, FN1, FN2)			\
L1                133 security/apparmor/include/perms.h 	xcheck(fn_for_each((L1), (P), (FN1)), fn_for_each((L2), (P), (FN2)))
L1                352 tools/perf/util/mem-events.c 			if (lvl & P(LVL, L1 )) stats->ld_l1hit++;
L1                403 tools/perf/util/mem-events.c 			if (lvl & P(LVL, L1 )) stats->st_l1hit++;
L1                406 tools/perf/util/mem-events.c 			if (lvl & P(LVL, L1)) stats->st_l1miss++;