K0 258 arch/mips/kvm/entry.c UASM_i_LA(&p, K0, ST0_EXL | KSU_USER | ST0_BEV | ST0_KX_IF_64); K0 259 arch/mips/kvm/entry.c uasm_i_mtc0(&p, K0, C0_STATUS); K0 263 arch/mips/kvm/entry.c UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, guest_ebase), K1); K0 264 arch/mips/kvm/entry.c build_set_exc_base(&p, K0); K0 271 arch/mips/kvm/entry.c uasm_i_addiu(&p, K0, ZERO, ST0_EXL | KSU_USER | ST0_IE | ST0_KX_IF_64); K0 273 arch/mips/kvm/entry.c uasm_i_or(&p, K0, K0, V0); K0 274 arch/mips/kvm/entry.c uasm_i_mtc0(&p, K0, C0_STATUS); K0 310 arch/mips/kvm/entry.c UASM_i_MFC0(&p, K0, c0_kscratch(), pgd_reg); K0 311 arch/mips/kvm/entry.c UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, host_pgd), K1); K0 334 arch/mips/kvm/entry.c uasm_i_mfc0(&p, K0, C0_GUESTCTL0); K0 335 arch/mips/kvm/entry.c uasm_i_ins(&p, K0, V1, MIPS_GCTL0_GM_SHIFT, 1); K0 336 arch/mips/kvm/entry.c uasm_i_mtc0(&p, K0, C0_GUESTCTL0); K0 360 arch/mips/kvm/entry.c UASM_i_MFC0(&p, K0, C0_ENTRYHI); K0 361 arch/mips/kvm/entry.c UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, host_entryhi), K0 389 arch/mips/kvm/entry.c UASM_i_LW(&p, K0, 0, T3); K0 401 arch/mips/kvm/entry.c uasm_i_and(&p, K0, K0, T2); K0 403 arch/mips/kvm/entry.c uasm_i_andi(&p, K0, K0, MIPS_ENTRYHI_ASID); K0 418 arch/mips/kvm/entry.c uasm_i_mtc0(&p, K0, C0_ENTRYHI); K0 421 arch/mips/kvm/entry.c uasm_i_mtc0(&p, K0, C0_ENTRYHI); K0 432 arch/mips/kvm/entry.c if (i == K0 || i == K1) K0 439 arch/mips/kvm/entry.c UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, hi), K1); K0 440 arch/mips/kvm/entry.c uasm_i_mthi(&p, K0); K0 442 arch/mips/kvm/entry.c UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, lo), K1); K0 443 arch/mips/kvm/entry.c uasm_i_mtlo(&p, K0); K0 447 arch/mips/kvm/entry.c UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, gprs[K0]), K1); K0 485 arch/mips/kvm/entry.c UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu, arch.gprs[K0]), K1); K0 505 arch/mips/kvm/entry.c build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ K0 507 arch/mips/kvm/entry.c build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ K0 512 arch/mips/kvm/entry.c build_get_ptep(&p, K0, K1); K0 513 arch/mips/kvm/entry.c build_update_entries(&p, K0, K1); K0 522 arch/mips/kvm/entry.c UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu, arch.gprs[K0]), K1); K0 561 arch/mips/kvm/entry.c UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, gprs[K0]), K1); K0 609 arch/mips/kvm/entry.c if (i == K0 || i == K1) K0 640 arch/mips/kvm/entry.c UASM_i_MFC0(&p, K0, C0_EPC); K0 641 arch/mips/kvm/entry.c UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, pc), K1); K0 643 arch/mips/kvm/entry.c UASM_i_MFC0(&p, K0, C0_BADVADDR); K0 644 arch/mips/kvm/entry.c UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, host_cp0_badvaddr), K0 647 arch/mips/kvm/entry.c uasm_i_mfc0(&p, K0, C0_CAUSE); K0 648 arch/mips/kvm/entry.c uasm_i_sw(&p, K0, offsetof(struct kvm_vcpu_arch, host_cp0_cause), K1); K0 651 arch/mips/kvm/entry.c uasm_i_mfc0(&p, K0, C0_BADINSTR); K0 652 arch/mips/kvm/entry.c uasm_i_sw(&p, K0, offsetof(struct kvm_vcpu_arch, K0 657 arch/mips/kvm/entry.c uasm_i_mfc0(&p, K0, C0_BADINSTRP); K0 658 arch/mips/kvm/entry.c uasm_i_sw(&p, K0, offsetof(struct kvm_vcpu_arch, K0 669 arch/mips/kvm/entry.c uasm_i_or(&p, K0, V0, AT); K0 671 arch/mips/kvm/entry.c uasm_i_mtc0(&p, K0, C0_STATUS); K0 674 arch/mips/kvm/entry.c UASM_i_LA_mostly(&p, K0, (long)&ebase); K0 675 arch/mips/kvm/entry.c UASM_i_LW(&p, K0, uasm_rel_lo((long)&ebase), K0); K0 676 arch/mips/kvm/entry.c build_set_exc_base(&p, K0); K0 713 arch/mips/kvm/entry.c UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, host_entryhi), K0 715 arch/mips/kvm/entry.c UASM_i_MTC0(&p, K0, C0_ENTRYHI); K0 735 arch/mips/kvm/entry.c uasm_i_mfc0(&p, K0, C0_GUESTCTL0); K0 736 arch/mips/kvm/entry.c uasm_i_ins(&p, K0, ZERO, MIPS_GCTL0_GM_SHIFT, 1); K0 737 arch/mips/kvm/entry.c uasm_i_mtc0(&p, K0, C0_GUESTCTL0); K0 740 arch/mips/kvm/entry.c uasm_i_sw(&p, K0, K0 782 arch/mips/kvm/entry.c kvm_mips_build_restore_scratch(&p, K0, SP); K0 785 arch/mips/kvm/entry.c UASM_i_LA_mostly(&p, K0, (long)&hwrena); K0 786 arch/mips/kvm/entry.c uasm_i_lw(&p, K0, uasm_rel_lo((long)&hwrena), K0); K0 787 arch/mips/kvm/entry.c uasm_i_mtc0(&p, K0, C0_HWRENA); K0 881 arch/mips/kvm/entry.c uasm_i_or(&p, K0, V1, AT); K0 882 arch/mips/kvm/entry.c uasm_i_mtc0(&p, K0, C0_STATUS); K0 921 arch/mips/kvm/entry.c uasm_i_sra(&p, K0, V0, 2); K0 922 arch/mips/kvm/entry.c uasm_i_move(&p, V0, K0); K0 932 arch/mips/kvm/entry.c UASM_i_LA_mostly(&p, K0, (long)&hwrena); K0 933 arch/mips/kvm/entry.c uasm_i_lw(&p, K0, uasm_rel_lo((long)&hwrena), K0); K0 934 arch/mips/kvm/entry.c uasm_i_mtc0(&p, K0, C0_HWRENA); K0 362 arch/mips/mm/tlbex.c r.r1 = K0; K0 370 arch/mips/mm/tlbex.c UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG); K0 371 arch/mips/mm/tlbex.c UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT); K0 374 arch/mips/mm/tlbex.c UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); K0 377 arch/mips/mm/tlbex.c UASM_i_ADDU(p, K0, K0, K1); K0 379 arch/mips/mm/tlbex.c UASM_i_LA(p, K0, (long)&handler_reg_save); K0 382 arch/mips/mm/tlbex.c UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0); K0 383 arch/mips/mm/tlbex.c UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0); K0 399 arch/mips/mm/tlbex.c UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0); K0 400 arch/mips/mm/tlbex.c UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0); K0 419 arch/mips/mm/tlbex.c uasm_i_mfc0(&p, K0, C0_BADVADDR); K0 422 arch/mips/mm/tlbex.c uasm_i_srl(&p, K0, K0, 22); /* load delay */ K0 423 arch/mips/mm/tlbex.c uasm_i_sll(&p, K0, K0, 2); K0 424 arch/mips/mm/tlbex.c uasm_i_addu(&p, K1, K1, K0); K0 425 arch/mips/mm/tlbex.c uasm_i_mfc0(&p, K0, C0_CONTEXT); K0 427 arch/mips/mm/tlbex.c uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ K0 428 arch/mips/mm/tlbex.c uasm_i_addu(&p, K1, K1, K0); K0 429 arch/mips/mm/tlbex.c uasm_i_lw(&p, K0, 0, K1); K0 431 arch/mips/mm/tlbex.c uasm_i_mtc0(&p, K0, C0_ENTRYLO0); K0 1316 arch/mips/mm/tlbex.c htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, K0 1320 arch/mips/mm/tlbex.c htlb_info.huge_pte = K0; K0 1330 arch/mips/mm/tlbex.c uasm_i_dmfc0(&p, K0, C0_BADVADDR); K0 1332 arch/mips/mm/tlbex.c uasm_i_xor(&p, K0, K0, K1); K0 1333 arch/mips/mm/tlbex.c uasm_i_dsrl_safe(&p, K1, K0, 62); K0 1334 arch/mips/mm/tlbex.c uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); K0 1335 arch/mips/mm/tlbex.c uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); K0 1336 arch/mips/mm/tlbex.c uasm_i_or(&p, K0, K0, K1); K0 1337 arch/mips/mm/tlbex.c uasm_il_bnez(&p, &r, K0, label_leave); K0 1342 arch/mips/mm/tlbex.c build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ K0 1344 arch/mips/mm/tlbex.c build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ K0 1348 arch/mips/mm/tlbex.c build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); K0 1351 arch/mips/mm/tlbex.c build_get_ptep(&p, K0, K1); K0 1352 arch/mips/mm/tlbex.c build_update_entries(&p, K0, K1); K0 1362 arch/mips/mm/tlbex.c build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, K0 1367 arch/mips/mm/tlbex.c build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode); K0 1539 arch/mips/mm/tlbex.c uasm_i_dmfc0(&p, K0, C0_BADVADDR); K0 1540 arch/mips/mm/tlbex.c uasm_i_dsrl_safe(&p, K1, K0, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); K0 1544 arch/mips/mm/tlbex.c uasm_il_bgez(&p, &r, K0, label_large_segbits_fault); K0 1551 arch/mips/mm/tlbex.c uasm_i_lddir(&p, K0, K1, 3); /* global page dir */ K0 1553 arch/mips/mm/tlbex.c uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */ K0 1561 arch/mips/mm/tlbex.c uasm_i_lui(&p, K0, PM_DEFAULT_MASK >> 16); K0 1562 arch/mips/mm/tlbex.c uasm_i_ori(&p, K0, K0, PM_DEFAULT_MASK & 0xffff); K0 1563 arch/mips/mm/tlbex.c uasm_i_mtc0(&p, K0, C0_PAGEMASK); K0 1565 arch/mips/mm/tlbex.c uasm_i_ori(&p, K0, 0, PM_DEFAULT_MASK); K0 1566 arch/mips/mm/tlbex.c uasm_i_mtc0(&p, K0, C0_PAGEMASK); K0 1942 arch/mips/mm/tlbex.c build_r3000_tlbchange_handler_head(&p, K0, K1); K0 1943 arch/mips/mm/tlbex.c build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl); K0 1945 arch/mips/mm/tlbex.c build_make_valid(&p, &r, K0, K1, -1); K0 1946 arch/mips/mm/tlbex.c build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); K0 1972 arch/mips/mm/tlbex.c build_r3000_tlbchange_handler_head(&p, K0, K1); K0 1973 arch/mips/mm/tlbex.c build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs); K0 1975 arch/mips/mm/tlbex.c build_make_write(&p, &r, K0, K1, -1); K0 1976 arch/mips/mm/tlbex.c build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); K0 2002 arch/mips/mm/tlbex.c build_r3000_tlbchange_handler_head(&p, K0, K1); K0 2003 arch/mips/mm/tlbex.c build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm); K0 2005 arch/mips/mm/tlbex.c build_make_write(&p, &r, K0, K1, -1); K0 2006 arch/mips/mm/tlbex.c build_r3000_pte_reload_tlbwi(&p, K0, K1); K0 2122 arch/mips/mm/tlbex.c uasm_i_dmfc0(&p, K0, C0_BADVADDR); K0 2124 arch/mips/mm/tlbex.c uasm_i_xor(&p, K0, K0, K1); K0 2125 arch/mips/mm/tlbex.c uasm_i_dsrl_safe(&p, K1, K0, 62); K0 2126 arch/mips/mm/tlbex.c uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); K0 2127 arch/mips/mm/tlbex.c uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); K0 2128 arch/mips/mm/tlbex.c uasm_i_or(&p, K0, K0, K1); K0 2129 arch/mips/mm/tlbex.c uasm_il_bnez(&p, &r, K0, label_leave); K0 2290 arch/mips/mm/tlbex.c uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0)); K0 2291 arch/mips/mm/tlbex.c uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0)); K0 2292 arch/mips/mm/tlbex.c uasm_i_jr(&p, K0); K0 2346 arch/mips/mm/tlbex.c uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); K0 2347 arch/mips/mm/tlbex.c uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); K0 2348 arch/mips/mm/tlbex.c uasm_i_jr(&p, K0); K0 2403 arch/mips/mm/tlbex.c uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); K0 2404 arch/mips/mm/tlbex.c uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); K0 2405 arch/mips/mm/tlbex.c uasm_i_jr(&p, K0); K0 493 crypto/anubis.c u32 K0, K1, K2, K3; K0 497 crypto/anubis.c K0 = T4[(kappa[N - 1] >> 24) ]; K0 502 crypto/anubis.c K0 = T4[(kappa[i] >> 24) ] ^ K0 503 crypto/anubis.c (T5[(K0 >> 24) ] & 0xff000000U) ^ K0 504 crypto/anubis.c (T5[(K0 >> 16) & 0xff] & 0x00ff0000U) ^ K0 505 crypto/anubis.c (T5[(K0 >> 8) & 0xff] & 0x0000ff00U) ^ K0 506 crypto/anubis.c (T5[(K0 ) & 0xff] & 0x000000ffU); K0 524 crypto/anubis.c ctx->E[r][0] = K0; K0 281 drivers/staging/rtl8188eu/core/rtw_security.c pmicdata->L = pmicdata->K0; K0 290 drivers/staging/rtl8188eu/core/rtw_security.c pmicdata->K0 = secmicgetuint32(key); K0 228 drivers/staging/rtl8188eu/include/rtw_security.h u32 K0, K1; /* Key */ K0 270 drivers/staging/rtl8712/rtl871x_security.c pmicdata->L = pmicdata->K0; K0 279 drivers/staging/rtl8712/rtl871x_security.c pmicdata->K0 = secmicgetuint32(key); K0 192 drivers/staging/rtl8712/rtl871x_security.h u32 K0, K1; /* Key */ K0 344 drivers/staging/rtl8723bs/core/rtw_security.c pmicdata->L = pmicdata->K0; K0 353 drivers/staging/rtl8723bs/core/rtw_security.c pmicdata->K0 = secmicgetuint32(key); K0 278 drivers/staging/rtl8723bs/include/rtw_security.h u32 K0, K1; /* Key */