JPU               363 arch/sh/kernel/cpu/sh4a/setup-sh7343.c 	INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
JPU               387 arch/sh/kernel/cpu/sh4a/setup-sh7343.c 	  { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
JPU               409 arch/sh/kernel/cpu/sh4a/setup-sh7343.c 	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
JPU               576 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 	INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
JPU               601 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 	  { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
JPU               623 arch/sh/kernel/cpu/sh4a/setup-sh7722.c 	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
JPU               986 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 	INTC_VECT(JPU, 0x560),
JPU              1028 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 	    JPU, 0, 0, LCDC } },
JPU              1058 arch/sh/kernel/cpu/sh4a/setup-sh7724.c 	{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },