AR71XX_RESET_REG_MISC_INT_ENABLE  532 arch/mips/ath79/clock.c 	misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
AR71XX_RESET_REG_MISC_INT_ENABLE  534 arch/mips/ath79/clock.c 	ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
AR71XX_RESET_REG_MISC_INT_ENABLE   42 drivers/irqchip/irq-ath79-misc.c 		  __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
AR71XX_RESET_REG_MISC_INT_ENABLE   66 drivers/irqchip/irq-ath79-misc.c 	t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
AR71XX_RESET_REG_MISC_INT_ENABLE   67 drivers/irqchip/irq-ath79-misc.c 	__raw_writel(t | BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
AR71XX_RESET_REG_MISC_INT_ENABLE   70 drivers/irqchip/irq-ath79-misc.c 	__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
AR71XX_RESET_REG_MISC_INT_ENABLE   79 drivers/irqchip/irq-ath79-misc.c 	t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
AR71XX_RESET_REG_MISC_INT_ENABLE   80 drivers/irqchip/irq-ath79-misc.c 	__raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
AR71XX_RESET_REG_MISC_INT_ENABLE   83 drivers/irqchip/irq-ath79-misc.c 	__raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
AR71XX_RESET_REG_MISC_INT_ENABLE  125 drivers/irqchip/irq-ath79-misc.c 	__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);