IRQ_VIRT_BASE      42 arch/arm/mach-dove/bridge-regs.h #define IRQ_MASK_LOW		(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)
IRQ_VIRT_BASE      43 arch/arm/mach-dove/bridge-regs.h #define FIQ_MASK_LOW		(IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF)
IRQ_VIRT_BASE      44 arch/arm/mach-dove/bridge-regs.h #define ENDPOINT_MASK_LOW	(IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF)
IRQ_VIRT_BASE      45 arch/arm/mach-dove/bridge-regs.h #define IRQ_MASK_HIGH		(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)
IRQ_VIRT_BASE      46 arch/arm/mach-dove/bridge-regs.h #define FIQ_MASK_HIGH		(IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF)
IRQ_VIRT_BASE      47 arch/arm/mach-dove/bridge-regs.h #define ENDPOINT_MASK_HIGH	(IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
IRQ_VIRT_BASE      48 arch/arm/mach-dove/bridge-regs.h #define PCIE_INTERRUPT_MASK	(IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
IRQ_VIRT_BASE      43 arch/arm/mach-dove/irq.c static void __iomem *dove_irq_base = IRQ_VIRT_BASE;
IRQ_VIRT_BASE      68 arch/arm/mach-dove/irq.c 	orion_irq_init(1, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
IRQ_VIRT_BASE      69 arch/arm/mach-dove/irq.c 	orion_irq_init(33, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
IRQ_VIRT_BASE      27 arch/arm/mach-mv78xx0/irq.c static void __iomem *mv78xx0_irq_base = IRQ_VIRT_BASE;
IRQ_VIRT_BASE      59 arch/arm/mach-mv78xx0/irq.c 	orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
IRQ_VIRT_BASE      60 arch/arm/mach-mv78xx0/irq.c 	orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
IRQ_VIRT_BASE      61 arch/arm/mach-mv78xx0/irq.c 	orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);