IRQENABLE_L1       46 arch/arm/mach-omap2/dma.c 	[IRQENABLE_L1]	= { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
IRQENABLE_L1     1252 arch/arm/plat-omap/dma.c 		p->dma_read(IRQENABLE_L1, 0);
IRQENABLE_L1     1268 arch/arm/plat-omap/dma.c 		IRQENABLE_L1, 0);
IRQENABLE_L1      663 drivers/dma/ti/omap-dma.c 			omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
IRQENABLE_L1      698 drivers/dma/ti/omap-dma.c 		omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
IRQENABLE_L1     1556 drivers/dma/ti/omap-dma.c 		omap_dma_glbl_write(od, IRQENABLE_L1, 0);