IRQENABLE_L0       45 arch/arm/mach-omap2/dma.c 	[IRQENABLE_L0]	= { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
IRQENABLE_L0      579 arch/arm/plat-omap/dma.c 	val = p->dma_read(IRQENABLE_L0, lch);
IRQENABLE_L0      581 arch/arm/plat-omap/dma.c 	p->dma_write(val, IRQENABLE_L0, lch);
IRQENABLE_L0      595 arch/arm/plat-omap/dma.c 	val = p->dma_read(IRQENABLE_L0, lch);
IRQENABLE_L0      597 arch/arm/plat-omap/dma.c 	p->dma_write(val, IRQENABLE_L0, lch);
IRQENABLE_L0     1220 arch/arm/plat-omap/dma.c 	enable_reg = p->dma_read(IRQENABLE_L0, 0);
IRQENABLE_L0     1250 arch/arm/plat-omap/dma.c 		p->dma_read(IRQENABLE_L0, 0);
IRQENABLE_L0     1266 arch/arm/plat-omap/dma.c 		IRQENABLE_L0, 0);
IRQENABLE_L0      665 drivers/dma/ti/omap-dma.c 			val = omap_dma_glbl_read(od, IRQENABLE_L0);
IRQENABLE_L0      667 drivers/dma/ti/omap-dma.c 			omap_dma_glbl_write(od, IRQENABLE_L0, val);
IRQENABLE_L0     1629 drivers/dma/ti/omap-dma.c 		omap_dma_glbl_write(od, IRQENABLE_L0, 0);